Owen Anderson
fd9085dca3
Tabs --> spaces.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:38:05 +00:00
Owen Anderson
10cbaab7b7
Cleanups based on Nick Lewycky's feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:36:48 +00:00
Owen Anderson
e66ef2d5f5
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:21:20 +00:00
Rafael Espindola
f5ade5d39a
Add support for the R and Q constraints.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 16:26:42 +00:00
Bruno Cardoso Lopes
155a92a491
Fix a bug in vpermilps mask checking. Fix PR10560
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 01:54:17 +00:00
Owen Anderson
33e57515b1
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen
c70c2cafe1
Promote VMOVS to VMOVD when possible.
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On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
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vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:41:44 +00:00
Owen Anderson
de317f40f7
Tighten operand checking of register-shifted-register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:33:27 +00:00
Bruno Cardoso Lopes
d40aa24ebf
Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:27:13 +00:00
Owen Anderson
c36481c474
Tighten operand checking on memory barrier instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:25:42 +00:00
Owen Anderson
35008c2f8d
Tighten operand checking on CPS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:05:39 +00:00
Owen Anderson
51c9805c4b
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes
18deb04e9c
Add v16i16 and v32i8 store patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:39:53 +00:00
Bruno Cardoso Lopes
cde4a1abd5
Use fp unpack instructions to unpack int types. Until we have AVX2, this
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is the best we can do for these patterns. This fix PR10554.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:18:37 +00:00
Eli Friedman
fc430a662f
Fix a couple ridiculous copy-paste errors. rdar://9914773 .
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:17:39 +00:00
Benjamin Kramer
793b811c50
ARM Disassembler: sign extend branch immediates.
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Not sure about BLXi, but this is what the old disassembler did.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:02:50 +00:00
Owen Anderson
51157d2234
Silence an false-positive warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:38:14 +00:00
Owen Anderson
65e95d950d
Don't generate the old-style disassembler in CMake builds either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:36:11 +00:00
Benjamin Kramer
9bd7c2836e
The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:34:19 +00:00
Owen Anderson
ad0d36b79f
Don't continue generating the old-style decoder file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:30:29 +00:00
Jim Grosbach
6cd5716f61
ARM fix typo in pre-indexed store lowering.
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rdar://9915869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:22:41 +00:00
Owen Anderson
e6afbabb63
Attempt to fix CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137147 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:09:59 +00:00
Owen Anderson
bd9091c18d
Tighten Thumb1 branch predicate decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:07:45 +00:00
Owen Anderson
8d7d2e1238
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 20:55:18 +00:00
Bill Wendling
c6fbe5636d
Revert r137134. It breaks some code as Eli pointed out.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 18:56:35 +00:00
Bill Wendling
a0f596c1fc
Print out the variable declaration only if it is a declaration. Otherwise, a
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'static' variable will be emitted twice.
PR10081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 18:31:50 +00:00
Bruno Cardoso Lopes
e2406dfd89
Reapply a more appropriate solution than in r137114. AVX supports
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v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
a511b8e519
Revert r137114
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 17:39:01 +00:00
Justin Holewinski
4bdd4ed564
PTX: Add initial support for device function calls
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- Calls are supported on SM 2.0+ for function with no return values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 17:36:31 +00:00
Renato Golin
719927a68f
Emitting ARM build attributes and values as ULEB, rather than char.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 09:50:10 +00:00
Bruno Cardoso Lopes
e321d7ffc5
Handle sitofp between v4f64 <- v4i32. Fix PR10559
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 05:48:01 +00:00
Bruno Cardoso Lopes
2f613c5fff
Add support for avx vector fextend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
a1dfb63b78
Add AVX versions of 128-bit sitofp and fptosi
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 03:04:25 +00:00
Bruno Cardoso Lopes
e5118ab7bb
Add two patterns to match special vmovss and vmovsd cases. Also fix
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the patterns already there to be more strict regarding the predicate.
This fixes PR10558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 01:43:09 +00:00
Bill Wendling
54f1536927
Add missing attributes to the C++ backend's output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 00:47:30 +00:00
Bruno Cardoso Lopes
0f0e0a0e58
Make LowerVSETCC aware of AVX types and add patterns to match them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 00:46:57 +00:00
Jim Grosbach
3148a65490
ARM parsing and encoding for LDRBT instruction.
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Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 23:28:47 +00:00
Owen Anderson
648f9a75fd
Thumb1 BL instructions encoding 22 bits of displacement, not 21.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 23:25:22 +00:00
Jakob Stoklund Olesen
36ee0e6405
Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
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They improve the verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 21:45:32 +00:00
Bruno Cardoso Lopes
328a9d4a0f
Add support for several vector shifts operations while in AVX mode. Fix PR10581
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 21:31:08 +00:00
Jim Grosbach
09176e10db
ARM load/store label parsing.
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Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:59:31 +00:00
Jakob Stoklund Olesen
2df3f58a0b
Hoist hasLoadFromStackSlot and hasStoreToStackSlot.
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These the methods are target-independent since they simply scan the
memory operands. They can live in TargetInstrInfoImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:53:24 +00:00
Owen Anderson
6d74631062
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:42:17 +00:00
Eli Friedman
2cb1dfa446
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 19:49:37 +00:00
Benjamin Kramer
41ab14b725
Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
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- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 18:56:44 +00:00
Jakob Stoklund Olesen
66b0f515d5
Don't clobber pending ST regs when FP regs are killed.
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X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints. It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.
When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.
This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.
This fixes PR10602.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 17:15:43 +00:00
Jim Grosbach
0d6fac36ed
ARM load instruction shifted register index operands.
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Parsing and encoding for shifted index operands for load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 22:03:36 +00:00
Jim Grosbach
f4fa3d6e46
ARM indexed load assembly parsing and encoding.
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More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 21:28:30 +00:00
Jim Grosbach
19dec207fc
ARM refactor indexed store instructions.
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Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 20:35:44 +00:00
Jim Grosbach
16578b5088
ARM simplify the postidx_reg operand encoding.
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The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 16:11:38 +00:00