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4757 Commits

Author SHA1 Message Date
Andrew Lenharth
26ed8697d4 all but CAS working on x86 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47798 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 21:52:34 +00:00
Dale Johannesen
3c8b59c546 Add MVT::is128BitVector and is64BitVector. Shrink 
unaligned load/store code using them.  Per review
of unaligned load/store vector patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47782 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 03:40:57 +00:00
Evan Cheng
84d4a2b4ad Refactor / clean up code; remove td list scheduler special tie breaker (no real benefit). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47779 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 00:39:47 +00:00
Evan Cheng
05548eb174 Don't fill eh frames even though these are text sections. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47765 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 19:36:59 +00:00
Bill Wendling
97e3c01eb4 If we reload a virtual register that's already been assigned, we want to mark 
that instruction as its "last use". This fixes PR1925.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47758 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 18:52:01 +00:00
Evan Cheng
4f658e9e4b Fix PR2112: don't run loop aligner if target doesn't have a TargetLowering object. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47755 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 17:52:15 +00:00
Evan Cheng
bec2c0c7e1 No need for coalescer to update kills. Only copies are coalesced and those instructions will be deleted. Doh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47749 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 02:50:03 +00:00
Evan Cheng
8f14da172d Remove redundant #include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47748 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 02:49:15 +00:00
Dan Gohman
6c231501f8 More APInt-ification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47746 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 01:47:35 +00:00
Dan Gohman
c7773bf90e Use the new convertFromAPInt instead of convertFromZeroExtendedInteger, 
which allows more of the surrounding arithmetic to be done with APInt
instead of uint64_t.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47745 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 01:44:25 +00:00
Dan Gohman
c6f9a06238 Use the new APInt-enabled form of getConstant instead of converting 
an APInt into a uint64_t to call getConstant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47742 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-29 01:41:59 +00:00
Evan Cheng
d703ed6aed Added option -align-loops=<true/false> to disable loop aligner pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47736 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 23:29:57 +00:00
Dale Johannesen
28d08fdb9f Interface of getByValTypeAlignment differed between 
generic & x86 versions; change generic to follow x86
and improve comments.  Add PPC version (not right
for non-Darwin.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47734 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 22:31:51 +00:00
Dale Johannesen
cd9f1747ab Fix an assertion message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47722 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 18:36:51 +00:00
Evan Cheng
643afa55e7 Keep track how many commutes are performed by the scheduler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47710 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 07:40:24 +00:00
Chris Lattner
e07415d400 implement expand for ISD::DECLARE by just deleting it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47708 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 05:53:40 +00:00
Evan Cheng
fb8075d03f Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47703 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-28 00:43:03 +00:00
Dale Johannesen
8155d64c2f Handle load/store of misaligned vectors that are the 
same size as an int type by doing a bitconvert of
load/store of the int type (same algorithm as floating point).
This makes them work for ppc Altivec.  There was some
code that purported to handle loads of (some) vectors
by splitting them into two smaller vectors, but getExtLoad
rejects subvector loads, so this could never have worked;
the patch removes it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47696 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 22:36:00 +00:00
Evan Cheng
21b3f31f8f Fix a bug in dead spill slot elimination. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47687 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 19:57:11 +00:00
Dan Gohman
18714aeaed Remove the `else', at Evan's insistence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47686 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 19:44:57 +00:00
Duncan Sands
052e976f85 Add a FIXME about the VECTOR_SHUFFLE evil hack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47676 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 17:39:13 +00:00
Duncan Sands
077f9b20d0 LegalizeTypes support for EXTRACT_VECTOR_ELT. The 
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value.  This puts more pressure on bitcast legalization,
and I've added the appropriate cases.  They needed to
be added anyway since users can generate such bitcasts
too if they want to.  Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.

<       subl    $92, %esp
<       movaps  %xmm0, 64(%esp)
<       movaps  %xmm0, (%esp)
<       movl    4(%esp), %eax
<       movl    %eax, 28(%esp)
<       movl    (%esp), %eax
<       movl    %eax, 24(%esp)
<       movq    24(%esp), %mm0
<       movq    %mm0, 56(%esp)
---
>       subl    $44, %esp
>       movaps  %xmm0, 16(%esp)
>       pshufd  $1, %xmm0, %xmm1
>       movd    %xmm1, 4(%esp)
>       movd    %xmm0, (%esp)
>       movq    (%esp), %mm0
>       movq    %mm0, 8(%esp)

<       subl    $92, %esp
<       movaps  %xmm0, 64(%esp)
<       movaps  %xmm0, (%esp)
<       movl    12(%esp), %eax
<       movl    %eax, 28(%esp)
<       movl    8(%esp), %eax
<       movl    %eax, 24(%esp)
<       movq    24(%esp), %mm0
<       movq    %mm0, 56(%esp)
---
>       subl    $44, %esp
>       movaps  %xmm0, 16(%esp)
>       pshufd  $3, %xmm0, %xmm1
>       movd    %xmm1, 4(%esp)
>       movhlps %xmm0, %xmm0
>       movd    %xmm0, (%esp)
>       movq    (%esp), %mm0
>       movq    %mm0, 8(%esp)

<       subl    $92, %esp
<       movaps  %xmm0, 64(%esp)
---
>       subl    $44, %esp

<       movl    16(%esp), %eax
<       movl    %eax, 48(%esp)
<       movl    20(%esp), %eax
<       movl    %eax, 52(%esp)
<       movaps  %xmm0, (%esp)
<       movl    4(%esp), %eax
<       movl    %eax, 60(%esp)
<       movl    (%esp), %eax
<       movl    %eax, 56(%esp)
---
>       pshufd  $1, %xmm0, %xmm1
>       movd    %xmm1, 4(%esp)
>       movd    %xmm0, (%esp)
>       movd    %xmm1, 12(%esp)
>       movd    %xmm0, 8(%esp)

<       subl    $92, %esp
<       movaps  %xmm0, 64(%esp)
---
>       subl    $44, %esp

<       movl    24(%esp), %eax
<       movl    %eax, 48(%esp)
<       movl    28(%esp), %eax
<       movl    %eax, 52(%esp)
<       movaps  %xmm0, (%esp)
<       movl    12(%esp), %eax
<       movl    %eax, 60(%esp)
<       movl    8(%esp), %eax
<       movl    %eax, 56(%esp)
---
>       pshufd  $3, %xmm0, %xmm1
>       movd    %xmm1, 4(%esp)
>       movhlps %xmm0, %xmm0
>       movd    %xmm0, (%esp)
>       movd    %xmm1, 12(%esp)
>       movd    %xmm0, 8(%esp)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 13:34:40 +00:00
Duncan Sands
8745b52853 LegalizeTypes support for legalizing the mask 
operand of a VECTOR_SHUFFLE.  The mask is a
vector of constant integers.  The code in
LegalizeDAG doesn't bother to legalize the
mask, since it's basically just storage for
a bunch of constants, however LegalizeTypes
is more picky.  The problem is that there may
not exist any legal vector-of-integers type
with a legal element type, so it is impossible
to create a legal mask!  Unless of course you
cheat by creating a BUILD_VECTOR where the
operands have a different type to the element
type of the vector being built...  This is
pretty ugly but works - all relevant tests in
the testsuite pass, and produce the same
assembler with and without LegalizeTypes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47670 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 13:03:44 +00:00
Duncan Sands
4f069e6db1 LegalizeTypes support for INSERT_VECTOR_ELT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47669 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 10:18:23 +00:00
Evan Cheng
be680dcea6 Don't track max alignment during stack object allocations since they can be deleted later. Let PEI compute it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47668 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 10:04:56 +00:00
Duncan Sands
e90a615f37 Support for legalizing MEMBARRIER. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47667 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 08:53:44 +00:00
Bill Wendling
6ef781f3ce Final de-tabification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 06:33:05 +00:00
Evan Cheng
d36531249a Spiller now remove unused spill slots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47657 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 03:04:06 +00:00
Dan Gohman
1953ecb0a6 Teach Legalize how to expand an EXTRACT_ELEMENT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47656 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 01:52:30 +00:00
Dan Gohman
b3564aa836 Convert the last remaining users of the non-APInt form of 
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 01:23:58 +00:00
Dan Gohman
7b8d4a9eef Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. 
Change several cases in SimplifyDemandedMask that don't ever do any
simplifying to reuse the logic in ComputeMaskedBits instead of
duplicating it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47648 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-27 00:25:32 +00:00
Chris Lattner
fe42462164 Use a smallvector for inactiveCounts and initialize it lazily 
instead of init'ing it maximally to zeros on entry.  getFreePhysReg
is pretty hot and only a few elements are typically used.  This speeds
up linscan by 5% on 176.gcc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47631 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 22:08:41 +00:00
Bill Wendling
e6d088acc9 Rename PrintableName to Name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 21:47:57 +00:00
Bill Wendling
74ab84c31e Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool 
would have been a Godsend here!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 21:11:01 +00:00
Evan Cheng
4d535cadf1 Enable -coalescer-commute-instrs by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47623 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 20:40:22 +00:00
Dan Gohman
d4cf992230 Avoid aborting on invalid shift counts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47612 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 18:50:50 +00:00
Chris Lattner
aeecb6c73a Fix PR2096, a regression introduced with my patch last night. This 
also fixes cfrac, flops, and 175.vpr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47605 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 17:09:59 +00:00
Duncan Sands
212a11c417 Fix a nasty bug in LegalizeTypes (spotted in 
CodeGen/PowerPC/illegal-element-type.ll): suppose
a node X is processed, and processing maps it to
a node Y.  Then X continues to exist in the DAG,
but with no users.  While processing some other
node, a new node may be created that happens to
be equal to X, and thus X will be reused rather
than a truly new node.  This can cause X to
"magically reappear", and since it is in the
Processed state in will not be reprocessed, so
at the end of type legalization the illegal node
X can still be present.  The solution is to replace
X with Y whenever X gets resurrected like this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47601 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 11:21:42 +00:00
Bill Wendling
f059deb8dd De-tabify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47598 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 10:51:52 +00:00
Evan Cheng
c886c460e4 This is possible: 
vr1 = extract_subreg vr2, 3
...
vr3 = extract_subreg vr1, 2
The end result is vr3 is equal to vr2 with subidx 2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47592 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 08:03:41 +00:00
Chris Lattner
0254e7033a Fix isNegatibleForFree to not return true for ConstantFP nodes 
after legalize.  Just because a constant is legal (e.g. 0.0 in SSE) 
doesn't mean that its negated value is legal (-0.0).  We could make
this stronger by checking to see if the negated constant is actually
legal post negation, but it doesn't seem like a big deal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47591 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 07:04:54 +00:00
Evan Cheng
5c80760fdf Refactor inline asm constraint matching code out of SDIsel into TargetLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47587 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-26 02:33:44 +00:00
Dan Gohman
f6283fd27b Make some static variables const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47566 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-25 21:39:34 +00:00
Dan Gohman
2e68b6f52d Convert MaskedValueIsZero and all its users to use APInt. Also add 
a SignBitIsZero function to simplify a common use case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47561 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-25 21:11:39 +00:00
Evan Cheng
e83a27516c All remat'ed loads cannot be folded into two-address code. Not just argument loads. This change doesn't really have any impact on codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47557 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-25 19:24:01 +00:00
Duncan Sands
1a9c9df1db In debug builds check that the key property holds: all 
result and operand types are legal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47546 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-25 16:21:21 +00:00
Evan Cheng
79a0c1e46c Correctly determine whether a argument load can be folded into its uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47545 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-25 08:50:41 +00:00
Duncan Sands
14fd63cae8 Add support to LegalizeTypes for building legal vectors 
out of illegal elements (BUILD_VECTOR).  Uses and beefs
up BUILD_PAIR, though it didn't really have to.  Like
most of LegalizeTypes, does not support soft-float.
This cures all "make check" vector building failures.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47537 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-24 07:36:03 +00:00
Bill Wendling
181eb737b2 Some platforms use the same name for 32-bit and 64-bit registers (like 
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-24 00:56:13 +00:00
Evan Cheng
249ded3fa8 Rematerialization logic was overly conservative when it comes to loads from fixed stack slots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47529 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-23 03:38:34 +00:00