6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-26 23:29:22 +00:00
Code Issues Projects Releases Wiki Activity
117,902 Commits 39 Branches 0 Tags 277 MiB
fe195d78dd
Commit Graph

4 Commits

Author SHA1 Message Date
Hal Finkel
6c81b118ca Add triple to test/CodeGen/PowerPC/stfiwx-2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178486 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-01 18:18:44 +00:00
Hal Finkel
4647919784 Add more PPC floating-point conversion instructions 
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-01 17:52:07 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-09 00:09:15 +00:00
Chris Lattner
a7a02fb828 Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to: 
_test:
	fctiwz f0, f1
	stfiwx f0, 0, r4
	blr 

instead of:

_test:
	fctiwz f0, f1
	stfd f0, -8(r1)
	nop
	nop
	lwz r2, -4(r1)
	stb r2, 0(r4)
	blr 

The former is not correct (stores 4 bytes, not 1).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46161 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-01-18 16:54:56 +00:00