//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// #include "ARMFPUName.h" #include "ARMFeatures.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMArchName.h" #include "MCTargetDesc/ARMBaseInfo.h" #include "MCTargetDesc/ARMMCExpr.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Support/ARMBuildAttributes.h" #include "llvm/Support/ARMEHABI.h" #include "llvm/Support/COFF.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ELF.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { class ARMOperand; enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; class UnwindContext { MCAsmParser &Parser; typedef SmallVector Locs; Locs FnStartLocs; Locs CantUnwindLocs; Locs PersonalityLocs; Locs PersonalityIndexLocs; Locs HandlerDataLocs; int FPReg; public: UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} bool hasFnStart() const { return !FnStartLocs.empty(); } bool cantUnwind() const { return !CantUnwindLocs.empty(); } bool hasHandlerData() const { return !HandlerDataLocs.empty(); } bool hasPersonality() const { return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); } void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } void saveFPReg(int Reg) { FPReg = Reg; } int getFPReg() const { return FPReg; } void emitFnStartLocNotes() const { for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); FI != FE; ++FI) Parser.Note(*FI, ".fnstart was specified here"); } void emitCantUnwindLocNotes() const { for (Locs::const_iterator UI = CantUnwindLocs.begin(), UE = CantUnwindLocs.end(); UI != UE; ++UI) Parser.Note(*UI, ".cantunwind was specified here"); } void emitHandlerDataLocNotes() const { for (Locs::const_iterator HI = HandlerDataLocs.begin(), HE = HandlerDataLocs.end(); HI != HE; ++HI) Parser.Note(*HI, ".handlerdata was specified here"); } void emitPersonalityLocNotes() const { for (Locs::const_iterator PI = PersonalityLocs.begin(), PE = PersonalityLocs.end(), PII = PersonalityIndexLocs.begin(), PIE = PersonalityIndexLocs.end(); PI != PE || PII != PIE;) { if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) Parser.Note(*PI++, ".personality was specified here"); else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) Parser.Note(*PII++, ".personalityindex was specified here"); else llvm_unreachable(".personality and .personalityindex cannot be " "at the same location"); } } void reset() { FnStartLocs = Locs(); CantUnwindLocs = Locs(); PersonalityLocs = Locs(); HandlerDataLocs = Locs(); PersonalityIndexLocs = Locs(); FPReg = ARM::SP; } }; class ARMAsmParser : public MCTargetAsmParser { MCSubtargetInfo &STI; MCAsmParser &Parser; const MCInstrInfo &MII; const MCRegisterInfo *MRI; UnwindContext UC; ARMTargetStreamer &getTargetStreamer() { MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); return static_cast(TS); } // Map of register aliases registers via the .req directive. StringMap RegisterReqs; bool NextSymbolIsThumb; struct { ARMCC::CondCodes Cond; // Condition for IT block. unsigned Mask:4; // Condition mask for instructions. // Starting at first 1 (from lsb). // '1' condition as indicated in IT. // '0' inverse of condition (else). // Count of instructions in IT block is // 4 - trailingzeroes(mask) bool FirstCond; // Explicit flag for when we're parsing the // First instruction in the IT block. It's // implied in the mask, so needs special // handling. unsigned CurPosition; // Current position in parsing of IT // block. In range [0,3]. Initialized // according to count of instructions in block. // ~0U if no active IT block. } ITState; bool inITBlock() { return ITState.CurPosition != ~0U;} void forwardITPosition() { if (!inITBlock()) return; // Move to the next instruction in the IT block, if there is one. If not, // mark the block as done. unsigned TZ = countTrailingZeros(ITState.Mask); if (++ITState.CurPosition == 5 - TZ) ITState.CurPosition = ~0U; // Done with the IT block after this. } MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } void Note(SMLoc L, const Twine &Msg, ArrayRef Ranges = None) { return Parser.Note(L, Msg, Ranges); } bool Warning(SMLoc L, const Twine &Msg, ArrayRef Ranges = None) { return Parser.Warning(L, Msg, Ranges); } bool Error(SMLoc L, const Twine &Msg, ArrayRef Ranges = None) { return Parser.Error(L, Msg, Ranges); } int tryParseRegister(); bool tryParseRegisterWithWriteBack(OperandVector &); int tryParseShiftRegister(OperandVector &); bool parseRegisterList(OperandVector &); bool parseMemory(OperandVector &); bool parseOperand(OperandVector &, StringRef Mnemonic); bool parsePrefix(ARMMCExpr::VariantKind &RefKind); bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, unsigned &ShiftAmount); bool parseLiteralValues(unsigned Size, SMLoc L); bool parseDirectiveThumb(SMLoc L); bool parseDirectiveARM(SMLoc L); bool parseDirectiveThumbFunc(SMLoc L); bool parseDirectiveCode(SMLoc L); bool parseDirectiveSyntax(SMLoc L); bool parseDirectiveReq(StringRef Name, SMLoc L); bool parseDirectiveUnreq(SMLoc L); bool parseDirectiveArch(SMLoc L); bool parseDirectiveEabiAttr(SMLoc L); bool parseDirectiveCPU(SMLoc L); bool parseDirectiveFPU(SMLoc L); bool parseDirectiveFnStart(SMLoc L); bool parseDirectiveFnEnd(SMLoc L); bool parseDirectiveCantUnwind(SMLoc L); bool parseDirectivePersonality(SMLoc L); bool parseDirectiveHandlerData(SMLoc L); bool parseDirectiveSetFP(SMLoc L); bool parseDirectivePad(SMLoc L); bool parseDirectiveRegSave(SMLoc L, bool IsVector); bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); bool parseDirectiveLtorg(SMLoc L); bool parseDirectiveEven(SMLoc L); bool parseDirectivePersonalityIndex(SMLoc L); bool parseDirectiveUnwindRaw(SMLoc L); bool parseDirectiveTLSDescSeq(SMLoc L); bool parseDirectiveMovSP(SMLoc L); bool parseDirectiveObjectArch(SMLoc L); bool parseDirectiveArchExtension(SMLoc L); bool parseDirectiveAlign(SMLoc L); bool parseDirectiveThumbSet(SMLoc L); StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, bool &CarrySetting, unsigned &ProcessorIMod, StringRef &ITMask); void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode); bool isThumb() const { // FIXME: Can tablegen auto-generate this? return (STI.getFeatureBits() & ARM::ModeThumb) != 0; } bool isThumbOne() const { return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; } bool isThumbTwo() const { return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); } bool hasThumb() const { return STI.getFeatureBits() & ARM::HasV4TOps; } bool hasV6Ops() const { return STI.getFeatureBits() & ARM::HasV6Ops; } bool hasV6MOps() const { return STI.getFeatureBits() & ARM::HasV6MOps; } bool hasV7Ops() const { return STI.getFeatureBits() & ARM::HasV7Ops; } bool hasV8Ops() const { return STI.getFeatureBits() & ARM::HasV8Ops; } bool hasARM() const { return !(STI.getFeatureBits() & ARM::FeatureNoARM); } void SwitchMode() { unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); setAvailableFeatures(FB); } bool isMClass() const { return STI.getFeatureBits() & ARM::FeatureMClass; } /// @name Auto-generated Match Functions /// { #define GET_ASSEMBLER_HEADER #include "ARMGenAsmMatcher.inc" /// } OperandMatchResultTy parseITCondCode(OperandVector &); OperandMatchResultTy parseCoprocNumOperand(OperandVector &); OperandMatchResultTy parseCoprocRegOperand(OperandVector &); OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); OperandMatchResultTy parseMSRMaskOperand(OperandVector &); OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, int High); OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { return parsePKHImm(O, "lsl", 0, 31); } OperandMatchResultTy parsePKHASRImm(OperandVector &O) { return parsePKHImm(O, "asr", 1, 32); } OperandMatchResultTy parseSetEndImm(OperandVector &); OperandMatchResultTy parseShifterImm(OperandVector &); OperandMatchResultTy parseRotImm(OperandVector &); OperandMatchResultTy parseBitfield(OperandVector &); OperandMatchResultTy parsePostIdxReg(OperandVector &); OperandMatchResultTy parseAM3Offset(OperandVector &); OperandMatchResultTy parseFPImm(OperandVector &); OperandMatchResultTy parseVectorList(OperandVector &); OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc); // Asm Match Converter Methods void cvtThumbMultiply(MCInst &Inst, const OperandVector &); void cvtThumbBranches(MCInst &Inst, const OperandVector &); bool validateInstruction(MCInst &Inst, const OperandVector &Ops); bool processInstruction(MCInst &Inst, const OperandVector &Ops); bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); public: enum ARMMatchResultTy { Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, Match_RequiresNotITBlock, Match_RequiresV6, Match_RequiresThumb2, #define GET_OPERAND_DIAGNOSTIC_TYPES #include "ARMGenAsmMatcher.inc" }; ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) { MCAsmParserExtension::Initialize(_Parser); // Cache the MCRegisterInfo. MRI = getContext().getRegisterInfo(); // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); // Not in an ITBlock to start with. ITState.CurPosition = ~0U; NextSymbolIsThumb = false; } // Implementation of the MCTargetAsmParser interface: bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool ParseDirective(AsmToken DirectiveID) override; unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; unsigned checkTargetMatchPredicate(MCInst &Inst) override; bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) override; void onLabelParsed(MCSymbol *Symbol) override; }; } // end anonymous namespace namespace { /// ARMOperand - Instances of this class represent a parsed ARM machine /// operand. class ARMOperand : public MCParsedAsmOperand { enum KindTy { k_CondCode, k_CCOut, k_ITCondMask, k_CoprocNum, k_CoprocReg, k_CoprocOption, k_Immediate, k_MemBarrierOpt, k_InstSyncBarrierOpt, k_Memory, k_PostIndexRegister, k_MSRMask, k_ProcIFlags, k_VectorIndex, k_Register, k_RegisterList, k_DPRRegisterList, k_SPRRegisterList, k_VectorList, k_VectorListAllLanes, k_VectorListIndexed, k_ShiftedRegister, k_ShiftedImmediate, k_ShifterImmediate, k_RotateImmediate, k_BitfieldDescriptor, k_Token } Kind; SMLoc StartLoc, EndLoc, AlignmentLoc; SmallVector Registers; struct CCOp { ARMCC::CondCodes Val; }; struct CopOp { unsigned Val; }; struct CoprocOptionOp { unsigned Val; }; struct ITMaskOp { unsigned Mask:4; }; struct MBOptOp { ARM_MB::MemBOpt Val; }; struct ISBOptOp { ARM_ISB::InstSyncBOpt Val; }; struct IFlagsOp { ARM_PROC::IFlags Val; }; struct MMaskOp { unsigned Val; }; struct TokOp { const char *Data; unsigned Length; }; struct RegOp { unsigned RegNum; }; // A vector register list is a sequential list of 1 to 4 registers. struct VectorListOp { unsigned RegNum; unsigned Count; unsigned LaneIndex; bool isDoubleSpaced; }; struct VectorIndexOp { unsigned Val; }; struct ImmOp { const MCExpr *Val; }; /// Combined record for all forms of ARM address expressions. struct MemoryOp { unsigned BaseRegNum; // Offset is in OffsetReg or OffsetImm. If both are zero, no offset // was specified. const MCConstantExpr *OffsetImm; // Offset immediate value unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg unsigned ShiftImm; // shift for OffsetReg. unsigned Alignment; // 0 = no alignment specified // n = alignment in bytes (2, 4, 8, 16, or 32) unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) }; struct PostIdxRegOp { unsigned RegNum; bool isAdd; ARM_AM::ShiftOpc ShiftTy; unsigned ShiftImm; }; struct ShifterImmOp { bool isASR; unsigned Imm; }; struct RegShiftedRegOp { ARM_AM::ShiftOpc ShiftTy; unsigned SrcReg; unsigned ShiftReg; unsigned ShiftImm; }; struct RegShiftedImmOp { ARM_AM::ShiftOpc ShiftTy; unsigned SrcReg; unsigned ShiftImm; }; struct RotImmOp { unsigned Imm; }; struct BitfieldOp { unsigned LSB; unsigned Width; }; union { struct CCOp CC; struct CopOp Cop; struct CoprocOptionOp CoprocOption; struct MBOptOp MBOpt; struct ISBOptOp ISBOpt; struct ITMaskOp ITMask; struct IFlagsOp IFlags; struct MMaskOp MMask; struct TokOp Tok; struct RegOp Reg; struct VectorListOp VectorList; struct VectorIndexOp VectorIndex; struct ImmOp Imm; struct MemoryOp Memory; struct PostIdxRegOp PostIdxReg; struct ShifterImmOp ShifterImm; struct RegShiftedRegOp RegShiftedReg; struct RegShiftedImmOp RegShiftedImm; struct RotImmOp RotImm; struct BitfieldOp Bitfield; }; public: ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { Kind = o.Kind; StartLoc = o.StartLoc; EndLoc = o.EndLoc; switch (Kind) { case k_CondCode: CC = o.CC; break; case k_ITCondMask: ITMask = o.ITMask; break; case k_Token: Tok = o.Tok; break; case k_CCOut: case k_Register: Reg = o.Reg; break; case k_RegisterList: case k_DPRRegisterList: case k_SPRRegisterList: Registers = o.Registers; break; case k_VectorList: case k_VectorListAllLanes: case k_VectorListIndexed: VectorList = o.VectorList; break; case k_CoprocNum: case k_CoprocReg: Cop = o.Cop; break; case k_CoprocOption: CoprocOption = o.CoprocOption; break; case k_Immediate: Imm = o.Imm; break; case k_MemBarrierOpt: MBOpt = o.MBOpt; break; case k_InstSyncBarrierOpt: ISBOpt = o.ISBOpt; case k_Memory: Memory = o.Memory; break; case k_PostIndexRegister: PostIdxReg = o.PostIdxReg; break; case k_MSRMask: MMask = o.MMask; break; case k_ProcIFlags: IFlags = o.IFlags; break; case k_ShifterImmediate: ShifterImm = o.ShifterImm; break; case k_ShiftedRegister: RegShiftedReg = o.RegShiftedReg; break; case k_ShiftedImmediate: RegShiftedImm = o.RegShiftedImm; break; case k_RotateImmediate: RotImm = o.RotImm; break; case k_BitfieldDescriptor: Bitfield = o.Bitfield; break; case k_VectorIndex: VectorIndex = o.VectorIndex; break; } } /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. SMLoc getEndLoc() const override { return EndLoc; } /// getLocRange - Get the range between the first and last token of this /// operand. SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } /// getAlignmentLoc - Get the location of the Alignment token of this operand. SMLoc getAlignmentLoc() const { assert(Kind == k_Memory && "Invalid access!"); return AlignmentLoc; } ARMCC::CondCodes getCondCode() const { assert(Kind == k_CondCode && "Invalid access!"); return CC.Val; } unsigned getCoproc() const { assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); return Cop.Val; } StringRef getToken() const { assert(Kind == k_Token && "Invalid access!"); return StringRef(Tok.Data, Tok.Length); } unsigned getReg() const override { assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); return Reg.RegNum; } const SmallVectorImpl &getRegList() const { assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList) && "Invalid access!"); return Registers; } const MCExpr *getImm() const { assert(isImm() && "Invalid access!"); return Imm.Val; } unsigned getVectorIndex() const { assert(Kind == k_VectorIndex && "Invalid access!"); return VectorIndex.Val; } ARM_MB::MemBOpt getMemBarrierOpt() const { assert(Kind == k_MemBarrierOpt && "Invalid access!"); return MBOpt.Val; } ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); return ISBOpt.Val; } ARM_PROC::IFlags getProcIFlags() const { assert(Kind == k_ProcIFlags && "Invalid access!"); return IFlags.Val; } unsigned getMSRMask() const { assert(Kind == k_MSRMask && "Invalid access!"); return MMask.Val; } bool isCoprocNum() const { return Kind == k_CoprocNum; } bool isCoprocReg() const { return Kind == k_CoprocReg; } bool isCoprocOption() const { return Kind == k_CoprocOption; } bool isCondCode() const { return Kind == k_CondCode; } bool isCCOut() const { return Kind == k_CCOut; } bool isITMask() const { return Kind == k_ITCondMask; } bool isITCondCode() const { return Kind == k_CondCode; } bool isImm() const override { return Kind == k_Immediate; } // checks whether this operand is an unsigned offset which fits is a field // of specified width and scaled by a specific number of bits template bool isUnsignedOffset() const { if (!isImm()) return false; if (isa(Imm.Val)) return true; if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) { int64_t Val = CE->getValue(); int64_t Align = 1LL << scale; int64_t Max = Align * ((1LL << width) - 1); return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); } return false; } // checks whether this operand is an signed offset which fits is a field // of specified width and scaled by a specific number of bits template bool isSignedOffset() const { if (!isImm()) return false; if (isa(Imm.Val)) return true; if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) { int64_t Val = CE->getValue(); int64_t Align = 1LL << scale; int64_t Max = Align * ((1LL << (width-1)) - 1); int64_t Min = -Align * (1LL << (width-1)); return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); } return false; } // checks whether this operand is a memory operand computed as an offset // applied to PC. the offset may have 8 bits of magnitude and is represented // with two bits of shift. textually it may be either [pc, #imm], #imm or // relocable expression... bool isThumbMemPC() const { int64_t Val = 0; if (isImm()) { if (isa(Imm.Val)) return true; const MCConstantExpr *CE = dyn_cast(Imm.Val); if (!CE) return false; Val = CE->getValue(); } else if (isMem()) { if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; if(Memory.BaseRegNum != ARM::PC) return false; Val = Memory.OffsetImm->getValue(); } else return false; return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); } bool isFPImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); return Val != -1; } bool isFBits16() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value <= 16; } bool isFBits32() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 1 && Value <= 32; } bool isImm8s4() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; } bool isImm0_1020s4() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; } bool isImm0_508s4() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ((Value & 3) == 0) && Value >= 0 && Value <= 508; } bool isImm0_508s4Neg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = -CE->getValue(); // explicitly exclude zero. we want that to use the normal 0_508 version. return ((Value & 3) == 0) && Value > 0 && Value <= 508; } bool isImm0_239() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 240; } bool isImm0_255() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 256; } bool isImm0_4095() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 4096; } bool isImm0_4095Neg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = -CE->getValue(); return Value > 0 && Value < 4096; } bool isImm0_1() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 2; } bool isImm0_3() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 4; } bool isImm0_7() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 8; } bool isImm0_15() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 16; } bool isImm0_31() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 32; } bool isImm0_63() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 64; } bool isImm8() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value == 8; } bool isImm16() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value == 16; } bool isImm32() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value == 32; } bool isShrImm8() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value <= 8; } bool isShrImm16() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value <= 16; } bool isShrImm32() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value <= 32; } bool isShrImm64() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value <= 64; } bool isImm1_7() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value < 8; } bool isImm1_15() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value < 16; } bool isImm1_31() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value < 32; } bool isImm1_16() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value < 17; } bool isImm1_32() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value < 33; } bool isImm0_32() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 33; } bool isImm0_65535() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 65536; } bool isImm256_65535Expr() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // If it's not a constant expression, it'll generate a fixup and be // handled later. if (!CE) return true; int64_t Value = CE->getValue(); return Value >= 256 && Value < 65536; } bool isImm0_65535Expr() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // If it's not a constant expression, it'll generate a fixup and be // handled later. if (!CE) return true; int64_t Value = CE->getValue(); return Value >= 0 && Value < 65536; } bool isImm24bit() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value <= 0xffffff; } bool isImmThumbSR() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value < 33; } bool isPKHLSLImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= 0 && Value < 32; } bool isPKHASRImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && Value <= 32; } bool isAdrLabel() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, but it can't fit // into shift immediate encoding, we reject it. if (isImm() && !isa(getImm())) return true; else return (isARMSOImm() || isARMSOImmNeg()); } bool isARMSOImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getSOImmVal(Value) != -1; } bool isARMSOImmNot() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getSOImmVal(~Value) != -1; } bool isARMSOImmNeg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); // Only use this when not representable as a plain so_imm. return ARM_AM::getSOImmVal(Value) == -1 && ARM_AM::getSOImmVal(-Value) != -1; } bool isT2SOImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getT2SOImmVal(Value) != -1; } bool isT2SOImmNot() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getT2SOImmVal(Value) == -1 && ARM_AM::getT2SOImmVal(~Value) != -1; } bool isT2SOImmNeg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); // Only use this when not representable as a plain so_imm. return ARM_AM::getT2SOImmVal(Value) == -1 && ARM_AM::getT2SOImmVal(-Value) != -1; } bool isSetEndImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value == 1 || Value == 0; } bool isReg() const override { return Kind == k_Register; } bool isRegList() const { return Kind == k_RegisterList; } bool isDPRRegList() const { return Kind == k_DPRRegisterList; } bool isSPRRegList() const { return Kind == k_SPRRegisterList; } bool isToken() const override { return Kind == k_Token; } bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } bool isMem() const override { return Kind == k_Memory; } bool isShifterImm() const { return Kind == k_ShifterImmediate; } bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } bool isRotImm() const { return Kind == k_RotateImmediate; } bool isBitfield() const { return Kind == k_BitfieldDescriptor; } bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } bool isPostIdxReg() const { return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; } bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { if (!isMem()) return false; // No offset of any kind. return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && (alignOK || Memory.Alignment == Alignment); } bool isMemPCRelImm12() const { if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base register must be PC. if (Memory.BaseRegNum != ARM::PC) return false; // Immediate offset in range [-4095, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); } bool isAlignedMemory() const { return isMemNoOffset(true); } bool isAlignedMemoryNone() const { return isMemNoOffset(false, 0); } bool isDupAlignedMemoryNone() const { return isMemNoOffset(false, 0); } bool isAlignedMemory16() const { if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory16() const { if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory32() const { if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory32() const { if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory64() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory64() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory64or128() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory64or128() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory64or128or256() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. return true; if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. return true; return isMemNoOffset(false, 0); } bool isAddrMode2() const { if (!isMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return true; // Immediate offset in range [-4095, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val > -4096 && Val < 4096; } bool isAM2OffsetImm() const { if (!isImm()) return false; // Immediate offset in range [-4095, 4095]. const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); } bool isAddrMode3() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isMem() || Memory.Alignment != 0) return false; // No shifts are legal for AM3. if (Memory.ShiftType != ARM_AM::no_shift) return false; // Check for register offset. if (Memory.OffsetRegNum) return true; // Immediate offset in range [-255, 255]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); // The #-0 offset is encoded as INT32_MIN, and we have to check // for this too. return (Val > -256 && Val < 256) || Val == INT32_MIN; } bool isAM3Offset() const { if (Kind != k_Immediate && Kind != k_PostIndexRegister) return false; if (Kind == k_PostIndexRegister) return PostIdxReg.ShiftTy == ARM_AM::no_shift; // Immediate offset in range [-255, 255]. const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); // Special case, #-0 is INT32_MIN. return (Val > -256 && Val < 256) || Val == INT32_MIN; } bool isAddrMode5() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return false; // Immediate offset in range [-1020, 1020] and a multiple of 4. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || Val == INT32_MIN; } bool isMemTBB() const { if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) return false; return true; } bool isMemTBH() const { if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || Memory.Alignment != 0 ) return false; return true; } bool isMemRegOffset() const { if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) return false; return true; } bool isT2MemRegOffset() const { if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.Alignment != 0) return false; // Only lsl #{0, 1, 2, 3} allowed. if (Memory.ShiftType == ARM_AM::no_shift) return true; if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) return false; return true; } bool isMemThumbRR() const { // Thumb reg+reg addressing is simple. Just two registers, a base and // an offset. No shifts, negations or any other complicating factors. if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) return false; return isARMLowRegister(Memory.BaseRegNum) && (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); } bool isMemThumbRIs4() const { if (!isMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 124]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 124 && (Val % 4) == 0; } bool isMemThumbRIs2() const { if (!isMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 62]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 62 && (Val % 2) == 0; } bool isMemThumbRIs1() const { if (!isMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset in range [0, 31]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 31; } bool isMemThumbSPI() const { if (!isMem() || Memory.OffsetRegNum != 0 || Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 1020]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 1020 && (Val % 4) == 0; } bool isMemImm8s4Offset() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset a multiple of 4 in range [-1020, 1020]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); // Special case, #-0 is INT32_MIN. return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; } bool isMemImm0_1020s4Offset() const { if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset a multiple of 4 in range [0, 1020]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 1020 && (Val & 3) == 0; } bool isMemImm8Offset() const { if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base reg of PC isn't allowed for these encodings. if (Memory.BaseRegNum == ARM::PC) return false; // Immediate offset in range [-255, 255]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val == INT32_MIN) || (Val > -256 && Val < 256); } bool isMemPosImm8Offset() const { if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [0, 255]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val < 256; } bool isMemNegImm8Offset() const { if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base reg of PC isn't allowed for these encodings. if (Memory.BaseRegNum == ARM::PC) return false; // Immediate offset in range [-255, -1]. if (!Memory.OffsetImm) return false; int64_t Val = Memory.OffsetImm->getValue(); return (Val == INT32_MIN) || (Val > -256 && Val < 0); } bool isMemUImm12Offset() const { if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [0, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val >= 0 && Val < 4096); } bool isMemImm12Offset() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [-4095, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); } bool isPostIdxImm8() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); return (Val > -256 && Val < 256) || (Val == INT32_MIN); } bool isPostIdxImm8s4() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || (Val == INT32_MIN); } bool isMSRMask() const { return Kind == k_MSRMask; } bool isProcIFlags() const { return Kind == k_ProcIFlags; } // NEON operands. bool isSingleSpacedVectorList() const { return Kind == k_VectorList && !VectorList.isDoubleSpaced; } bool isDoubleSpacedVectorList() const { return Kind == k_VectorList && VectorList.isDoubleSpaced; } bool isVecListOneD() const { if (!isSingleSpacedVectorList()) return false; return VectorList.Count == 1; } bool isVecListDPair() const { if (!isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairRegClassID] .contains(VectorList.RegNum)); } bool isVecListThreeD() const { if (!isSingleSpacedVectorList()) return false; return VectorList.Count == 3; } bool isVecListFourD() const { if (!isSingleSpacedVectorList()) return false; return VectorList.Count == 4; } bool isVecListDPairSpaced() const { if (Kind != k_VectorList) return false; if (isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] .contains(VectorList.RegNum)); } bool isVecListThreeQ() const { if (!isDoubleSpacedVectorList()) return false; return VectorList.Count == 3; } bool isVecListFourQ() const { if (!isDoubleSpacedVectorList()) return false; return VectorList.Count == 4; } bool isSingleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; } bool isDoubleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; } bool isVecListOneDAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 1; } bool isVecListDPairAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return (ARMMCRegisterClasses[ARM::DPairRegClassID] .contains(VectorList.RegNum)); } bool isVecListDPairSpacedAllLanes() const { if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 2; } bool isVecListThreeDAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 3; } bool isVecListThreeQAllLanes() const { if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 3; } bool isVecListFourDAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 4; } bool isVecListFourQAllLanes() const { if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 4; } bool isSingleSpacedVectorIndexed() const { return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; } bool isDoubleSpacedVectorIndexed() const { return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; } bool isVecListOneDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 7; } bool isVecListOneDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 3; } bool isVecListOneDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 1; } bool isVecListTwoDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 7; } bool isVecListTwoDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 3; } bool isVecListTwoQWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 1; } bool isVecListTwoQHWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 3; } bool isVecListTwoDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 1; } bool isVecListThreeDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 7; } bool isVecListThreeDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 3; } bool isVecListThreeQWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 1; } bool isVecListThreeQHWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 3; } bool isVecListThreeDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 1; } bool isVecListFourDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 7; } bool isVecListFourDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 3; } bool isVecListFourQWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 1; } bool isVecListFourQHWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 3; } bool isVecListFourDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 1; } bool isVectorIndex8() const { if (Kind != k_VectorIndex) return false; return VectorIndex.Val < 8; } bool isVectorIndex16() const { if (Kind != k_VectorIndex) return false; return VectorIndex.Val < 4; } bool isVectorIndex32() const { if (Kind != k_VectorIndex) return false; return VectorIndex.Val < 2; } bool isNEONi8splat() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = CE->getValue(); // i8 value splatted across 8 bytes. The immediate is just the 8 byte // value. return Value >= 0 && Value < 256; } bool isNEONi16splat() const { if (isNEONByteReplicate(2)) return false; // Leave that for bytes replication and forbid by default. if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = CE->getValue(); // i16 value in the range [0,255] or [0x0100, 0xff00] return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); } bool isNEONi32splat() const { if (isNEONByteReplicate(4)) return false; // Leave that for bytes replication and forbid by default. if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = CE->getValue(); // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00) || (Value >= 0x010000 && Value <= 0xff0000) || (Value >= 0x01000000 && Value <= 0xff000000); } bool isNEONByteReplicate(unsigned NumBytes) const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = CE->getValue(); if (!Value) return false; // Don't bother with zero. unsigned char B = Value & 0xff; for (unsigned i = 1; i < NumBytes; ++i) { Value >>= 8; if ((Value & 0xff) != B) return false; } return true; } bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); } bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); } bool isNEONi32vmov() const { if (isNEONByteReplicate(4)) return false; // Let it to be classified as byte-replicate case. if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = CE->getValue(); // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00) || (Value >= 0x010000 && Value <= 0xff0000) || (Value >= 0x01000000 && Value <= 0xff000000) || (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); } bool isNEONi32vmovNeg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = ~CE->getValue(); // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00) || (Value >= 0x010000 && Value <= 0xff0000) || (Value >= 0x01000000 && Value <= 0xff000000) || (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); } bool isNEONi64splat() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; uint64_t Value = CE->getValue(); // i64 value with each byte being either 0 or 0xff. for (unsigned i = 0; i < 8; ++i) if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; return true; } void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. if (!Expr) Inst.addOperand(MCOperand::CreateImm(0)); else if (const MCConstantExpr *CE = dyn_cast(Expr)) Inst.addOperand(MCOperand::CreateImm(CE->getValue())); else Inst.addOperand(MCOperand::CreateExpr(Expr)); } void addCondCodeOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; Inst.addOperand(MCOperand::CreateReg(RegNum)); } void addCoprocNumOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(getCoproc())); } void addCoprocRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(getCoproc())); } void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); } void addITMaskOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); } void addITCondCodeOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); } void addCCOutOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(getReg())); } void addRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(getReg())); } void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!"); Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); Inst.addOperand(MCOperand::CreateImm( ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); } void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!"); Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); // Shift of #32 is encoded as 0 where permitted unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); Inst.addOperand(MCOperand::CreateImm( ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); } void addShifterImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | ShifterImm.Imm)); } void addRegListOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const SmallVectorImpl &RegList = getRegList(); for (SmallVectorImpl::const_iterator I = RegList.begin(), E = RegList.end(); I != E; ++I) Inst.addOperand(MCOperand::CreateReg(*I)); } void addDPRRegListOperands(MCInst &Inst, unsigned N) const { addRegListOperands(Inst, N); } void addSPRRegListOperands(MCInst &Inst, unsigned N) const { addRegListOperands(Inst, N); } void addRotImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // Encoded as val>>3. The printer handles display as 8, 16, 24. Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); } void addBitfieldOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // Munge the lsb/width into a bitfield mask. unsigned lsb = Bitfield.LSB; unsigned width = Bitfield.Width; // Make a 32-bit mask w/ the referenced bits clear and all other bits set. uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> (32 - (lsb + width))); Inst.addOperand(MCOperand::CreateImm(Mask)); } void addImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); } void addFBits16Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); } void addFBits32Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); } void addFPImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); Inst.addOperand(MCOperand::CreateImm(Val)); } void addImm8s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // FIXME: We really want to scale the value here, but the LDRD/STRD // instruction don't encode operands that way yet. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(CE->getValue())); } void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate is scaled by four in the encoding and is stored // in the MCInst as such. Lop off the low two bits here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); } void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate is scaled by four in the encoding and is stored // in the MCInst as such. Lop off the low two bits here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); } void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate is scaled by four in the encoding and is stored // in the MCInst as such. Lop off the low two bits here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); } void addImm1_16Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The constant encodes as the immediate-1, and we store in the instruction // the bits as encoded, so subtract off one here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); } void addImm1_32Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The constant encodes as the immediate-1, and we store in the instruction // the bits as encoded, so subtract off one here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); } void addImmThumbSROperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The constant encodes as the immediate, except for 32, which encodes as // zero. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Imm = CE->getValue(); Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); } void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // An ASR value of 32 encodes as 0, so that's how we want to add it to // the instruction as well. const MCConstantExpr *CE = dyn_cast(getImm()); int Val = CE->getValue(); Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); } void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually a t2_so_imm, but we have its bitwise // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); } void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually a t2_so_imm, but we have its // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); } void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually an imm0_4095, but we have its // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); } void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { if(const MCConstantExpr *CE = dyn_cast(getImm())) { Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); return; } const MCSymbolRefExpr *SR = dyn_cast(Imm.Val); assert(SR && "Unknown value type!"); Inst.addOperand(MCOperand::CreateExpr(SR)); } void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); if (isImm()) { const MCConstantExpr *CE = dyn_cast(getImm()); if (CE) { Inst.addOperand(MCOperand::CreateImm(CE->getValue())); return; } const MCSymbolRefExpr *SR = dyn_cast(Imm.Val); assert(SR && "Unknown value type!"); Inst.addOperand(MCOperand::CreateExpr(SR)); return; } assert(isMem() && "Unknown value type!"); assert(isa(Memory.OffsetImm) && "Unknown value type!"); Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); } void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually a so_imm, but we have its bitwise // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); } void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually a so_imm, but we have its // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); } void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); } void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); } void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); } void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); int32_t Imm = Memory.OffsetImm->getValue(); Inst.addOperand(MCOperand::CreateImm(Imm)); } void addAdrLabelOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); assert(isImm() && "Not an immediate!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. if (!isa(getImm())) { Inst.addOperand(MCOperand::CreateExpr(getImm())); return; } const MCConstantExpr *CE = dyn_cast(getImm()); int Val = CE->getValue(); Inst.addOperand(MCOperand::CreateImm(Val)); } void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); } void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAddrMode2Operands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; if (!Memory.OffsetRegNum) { ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == INT32_MIN) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); } else { // For register offset, we encode the shift type and negation flag // here. Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, Memory.ShiftImm, Memory.ShiftType); } Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE && "non-constant AM2OffsetImm operand!"); int32_t Val = CE->getValue(); ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == INT32_MIN) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); Inst.addOperand(MCOperand::CreateReg(0)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addAddrMode3Operands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::CreateExpr(getImm())); Inst.addOperand(MCOperand::CreateReg(0)); Inst.addOperand(MCOperand::CreateImm(0)); return; } int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; if (!Memory.OffsetRegNum) { ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == INT32_MIN) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM3Opc(AddSub, Val); } else { // For register offset, we encode the shift type and negation flag // here. Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); } Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); if (Kind == k_PostIndexRegister) { int32_t Val = ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); return; } // Constant offset. const MCConstantExpr *CE = static_cast(getImm()); int32_t Val = CE->getValue(); ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == INT32_MIN) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM3Opc(AddSub, Val); Inst.addOperand(MCOperand::CreateReg(0)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addAddrMode5Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::CreateExpr(getImm())); Inst.addOperand(MCOperand::CreateImm(0)); return; } // The lower two bits are always zero and as such are not encoded. int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == INT32_MIN) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM5Opc(AddSub, Val); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::CreateExpr(getImm())); Inst.addOperand(MCOperand::CreateImm(0)); return; } int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // The lower two bits are always zero and as such are not encoded. int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { addMemImm8OffsetOperands(Inst, N); } void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { addMemImm8OffsetOperands(Inst, N); } void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If this is an immediate, it's a label reference. if (isImm()) { addExpr(Inst, getImm()); Inst.addOperand(MCOperand::CreateImm(0)); return; } // Otherwise, it's a normal memory reg+offset. int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If this is an immediate, it's a label reference. if (isImm()) { addExpr(Inst, getImm()); Inst.addOperand(MCOperand::CreateImm(0)); return; } // Otherwise, it's a normal memory reg+offset. int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemTBBOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); } void addMemTBHOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); } void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, Memory.ShiftImm, Memory.ShiftType); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); } void addMemThumbRROperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); } void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::CreateImm(Val)); } void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE && "non-constant post-idx-imm8 operand!"); int Imm = CE->getValue(); bool isAdd = Imm >= 0; if (Imm == INT32_MIN) Imm = 0; Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; Inst.addOperand(MCOperand::CreateImm(Imm)); } void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE && "non-constant post-idx-imm8s4 operand!"); int Imm = CE->getValue(); bool isAdd = Imm >= 0; if (Imm == INT32_MIN) Imm = 0; // Immediate is scaled by 4. Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; Inst.addOperand(MCOperand::CreateImm(Imm)); } void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); } void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); // The sign, shift type, and shift amount are encoded in a single operand // using the AM2 encoding helpers. ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, PostIdxReg.ShiftTy); Inst.addOperand(MCOperand::CreateImm(Imm)); } void addMSRMaskOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); } void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); } void addVecListOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); } void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); } void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); } void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); } void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); } void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. // Mask in that this is an i8 splat. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); } void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); if (Value >= 256) Value = (Value >> 8) | 0xa00; else Value |= 0x800; Inst.addOperand(MCOperand::CreateImm(Value)); } void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); if (Value >= 256 && Value <= 0xff00) Value = (Value >> 8) | 0x200; else if (Value > 0xffff && Value <= 0xff0000) Value = (Value >> 16) | 0x400; else if (Value > 0xffffff) Value = (Value >> 24) | 0x600; Inst.addOperand(MCOperand::CreateImm(Value)); } void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); assert((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && "All vmvn instructions that wants to replicate non-zero byte " "always must be replaced with VMOVv8i8 or VMOVv16i8."); unsigned B = ((~Value) & 0xff); B |= 0xe00; // cmode = 0b1110 Inst.addOperand(MCOperand::CreateImm(B)); } void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); if (Value >= 256 && Value <= 0xffff) Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); else if (Value > 0xffff && Value <= 0xffffff) Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); else if (Value > 0xffffff) Value = (Value >> 24) | 0x600; Inst.addOperand(MCOperand::CreateImm(Value)); } void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); assert((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte " "always must be replaced with VMOVv8i8 or VMOVv16i8."); unsigned B = Value & 0xff; B |= 0xe00; // cmode = 0b1110 Inst.addOperand(MCOperand::CreateImm(B)); } void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = ~CE->getValue(); if (Value >= 256 && Value <= 0xffff) Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); else if (Value > 0xffff && Value <= 0xffffff) Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); else if (Value > 0xffffff) Value = (Value >> 24) | 0x600; Inst.addOperand(MCOperand::CreateImm(Value)); } void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); uint64_t Value = CE->getValue(); unsigned Imm = 0; for (unsigned i = 0; i < 8; ++i, Value >>= 8) { Imm |= (Value & 1) << i; } Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); } void print(raw_ostream &OS) const override; static std::unique_ptr CreateITMask(unsigned Mask, SMLoc S) { auto Op = make_unique(k_ITCondMask); Op->ITMask.Mask = Mask; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { auto Op = make_unique(k_CondCode); Op->CC.Val = CC; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCoprocNum(unsigned CopVal, SMLoc S) { auto Op = make_unique(k_CoprocNum); Op->Cop.Val = CopVal; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCoprocReg(unsigned CopVal, SMLoc S) { auto Op = make_unique(k_CoprocReg); Op->Cop.Val = CopVal; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { auto Op = make_unique(k_CoprocOption); Op->Cop.Val = Val; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateCCOut(unsigned RegNum, SMLoc S) { auto Op = make_unique(k_CCOut); Op->Reg.RegNum = RegNum; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateToken(StringRef Str, SMLoc S) { auto Op = make_unique(k_Token); Op->Tok.Data = Str.data(); Op->Tok.Length = Str.size(); Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { auto Op = make_unique(k_Register); Op->Reg.RegNum = RegNum; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) { auto Op = make_unique(k_ShiftedRegister); Op->RegShiftedReg.ShiftTy = ShTy; Op->RegShiftedReg.SrcReg = SrcReg; Op->RegShiftedReg.ShiftReg = ShiftReg; Op->RegShiftedReg.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) { auto Op = make_unique(k_ShiftedImmediate); Op->RegShiftedImm.ShiftTy = ShTy; Op->RegShiftedImm.SrcReg = SrcReg; Op->RegShiftedImm.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateShifterImm(bool isASR, unsigned Imm, SMLoc S, SMLoc E) { auto Op = make_unique(k_ShifterImmediate); Op->ShifterImm.isASR = isASR; Op->ShifterImm.Imm = Imm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { auto Op = make_unique(k_RotateImmediate); Op->RotImm.Imm = Imm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { auto Op = make_unique(k_BitfieldDescriptor); Op->Bitfield.LSB = LSB; Op->Bitfield.Width = Width; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateRegList(SmallVectorImpl> &Regs, SMLoc StartLoc, SMLoc EndLoc) { assert (Regs.size() > 0 && "RegList contains no registers?"); KindTy Kind = k_RegisterList; if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) Kind = k_DPRRegisterList; else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. contains(Regs.front().second)) Kind = k_SPRRegisterList; // Sort based on the register encoding values. array_pod_sort(Regs.begin(), Regs.end()); auto Op = make_unique(Kind); for (SmallVectorImpl >::const_iterator I = Regs.begin(), E = Regs.end(); I != E; ++I) Op->Registers.push_back(I->second); Op->StartLoc = StartLoc; Op->EndLoc = EndLoc; return Op; } static std::unique_ptr CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) { auto Op = make_unique(k_VectorList); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) { auto Op = make_unique(k_VectorListAllLanes); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) { auto Op = make_unique(k_VectorListIndexed); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.LaneIndex = Index; Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { auto Op = make_unique(k_VectorIndex); Op->VectorIndex.Val = Idx; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { auto Op = make_unique(k_Immediate); Op->Imm.Val = Val; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) { auto Op = make_unique(k_Memory); Op->Memory.BaseRegNum = BaseRegNum; Op->Memory.OffsetImm = OffsetImm; Op->Memory.OffsetRegNum = OffsetRegNum; Op->Memory.ShiftType = ShiftType; Op->Memory.ShiftImm = ShiftImm; Op->Memory.Alignment = Alignment; Op->Memory.isNegative = isNegative; Op->StartLoc = S; Op->EndLoc = E; Op->AlignmentLoc = AlignmentLoc; return Op; } static std::unique_ptr CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) { auto Op = make_unique(k_PostIndexRegister); Op->PostIdxReg.RegNum = RegNum; Op->PostIdxReg.isAdd = isAdd; Op->PostIdxReg.ShiftTy = ShiftTy; Op->PostIdxReg.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { auto Op = make_unique(k_MemBarrierOpt); Op->MBOpt.Val = Opt; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { auto Op = make_unique(k_InstSyncBarrierOpt); Op->ISBOpt.Val = Opt; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { auto Op = make_unique(k_ProcIFlags); Op->IFlags.Val = IFlags; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateMSRMask(unsigned MMask, SMLoc S) { auto Op = make_unique(k_MSRMask); Op->MMask.Val = MMask; Op->StartLoc = S; Op->EndLoc = S; return Op; } }; } // end anonymous namespace. void ARMOperand::print(raw_ostream &OS) const { switch (Kind) { case k_CondCode: OS << ""; break; case k_CCOut: OS << ""; break; case k_ITCondMask: { static const char *const MaskStr[] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" }; assert((ITMask.Mask & 0xf) == ITMask.Mask); OS << ""; break; } case k_CoprocNum: OS << ""; break; case k_CoprocReg: OS << ""; break; case k_CoprocOption: OS << ""; break; case k_MSRMask: OS << ""; break; case k_Immediate: getImm()->print(OS); break; case k_MemBarrierOpt: OS << ""; break; case k_InstSyncBarrierOpt: OS << ""; break; case k_Memory: OS << ""; break; case k_PostIndexRegister: OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") << PostIdxReg.RegNum; if (PostIdxReg.ShiftTy != ARM_AM::no_shift) OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " << PostIdxReg.ShiftImm; OS << ">"; break; case k_ProcIFlags: { OS << "= 0; --i) if (IFlags & (1 << i)) OS << ARM_PROC::IFlagsToString(1 << i); OS << ">"; break; } case k_Register: OS << ""; break; case k_ShifterImmediate: OS << ""; break; case k_ShiftedRegister: OS << ""; break; case k_ShiftedImmediate: OS << ""; break; case k_RotateImmediate: OS << ""; break; case k_BitfieldDescriptor: OS << ""; break; case k_RegisterList: case k_DPRRegisterList: case k_SPRRegisterList: { OS << " &RegList = getRegList(); for (SmallVectorImpl::const_iterator I = RegList.begin(), E = RegList.end(); I != E; ) { OS << *I; if (++I < E) OS << ", "; } OS << ">"; break; } case k_VectorList: OS << ""; break; case k_VectorListAllLanes: OS << ""; break; case k_VectorListIndexed: OS << ""; break; case k_Token: OS << "'" << getToken() << "'"; break; case k_VectorIndex: OS << ""; break; } } /// @name Auto-generated Match Functions /// { static unsigned MatchRegisterName(StringRef Name); /// } bool ARMAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { StartLoc = Parser.getTok().getLoc(); EndLoc = Parser.getTok().getEndLoc(); RegNo = tryParseRegister(); return (RegNo == (unsigned)-1); } /// Try to parse a register name. The token must be an Identifier when called, /// and if it is a register name the token is eaten and the register number is /// returned. Otherwise return -1. /// int ARMAsmParser::tryParseRegister() { const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return -1; std::string lowerCase = Tok.getString().lower(); unsigned RegNum = MatchRegisterName(lowerCase); if (!RegNum) { RegNum = StringSwitch(lowerCase) .Case("r13", ARM::SP) .Case("r14", ARM::LR) .Case("r15", ARM::PC) .Case("ip", ARM::R12) // Additional register name aliases for 'gas' compatibility. .Case("a1", ARM::R0) .Case("a2", ARM::R1) .Case("a3", ARM::R2) .Case("a4", ARM::R3) .Case("v1", ARM::R4) .Case("v2", ARM::R5) .Case("v3", ARM::R6) .Case("v4", ARM::R7) .Case("v5", ARM::R8) .Case("v6", ARM::R9) .Case("v7", ARM::R10) .Case("v8", ARM::R11) .Case("sb", ARM::R9) .Case("sl", ARM::R10) .Case("fp", ARM::R11) .Default(0); } if (!RegNum) { // Check for aliases registered via .req. Canonicalize to lower case. // That's more consistent since register names are case insensitive, and // it's how the original entry was passed in from MC/MCParser/AsmParser. StringMap::const_iterator Entry = RegisterReqs.find(lowerCase); // If no match, return failure. if (Entry == RegisterReqs.end()) return -1; Parser.Lex(); // Eat identifier token. return Entry->getValue(); } Parser.Lex(); // Eat identifier token. return RegNum; } // Try to parse a shifter (e.g., "lsl "). On success, return 0. // If a recoverable error occurs, return 1. If an irrecoverable error // occurs, return -1. An irrecoverable error is one where tokens have been // consumed in the process of trying to parse the shifter (i.e., when it is // indeed a shifter operand, but malformed). int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return -1; std::string lowerCase = Tok.getString().lower(); ARM_AM::ShiftOpc ShiftTy = StringSwitch(lowerCase) .Case("asl", ARM_AM::lsl) .Case("lsl", ARM_AM::lsl) .Case("lsr", ARM_AM::lsr) .Case("asr", ARM_AM::asr) .Case("ror", ARM_AM::ror) .Case("rrx", ARM_AM::rrx) .Default(ARM_AM::no_shift); if (ShiftTy == ARM_AM::no_shift) return 1; Parser.Lex(); // Eat the operator. // The source register for the shift has already been added to the // operand list, so we need to pop it off and combine it into the shifted // register operand instead. std::unique_ptr PrevOp( (ARMOperand *)Operands.pop_back_val().release()); if (!PrevOp->isReg()) return Error(PrevOp->getStartLoc(), "shift must be of a register"); int SrcReg = PrevOp->getReg(); SMLoc EndLoc; int64_t Imm = 0; int ShiftReg = 0; if (ShiftTy == ARM_AM::rrx) { // RRX Doesn't have an explicit shift amount. The encoder expects // the shift register to be the same as the source register. Seems odd, // but OK. ShiftReg = SrcReg; } else { // Figure out if this is shifted by a constant or a register (for non-RRX). if (Parser.getTok().is(AsmToken::Hash) || Parser.getTok().is(AsmToken::Dollar)) { Parser.Lex(); // Eat hash. SMLoc ImmLoc = Parser.getTok().getLoc(); const MCExpr *ShiftExpr = nullptr; if (getParser().parseExpression(ShiftExpr, EndLoc)) { Error(ImmLoc, "invalid immediate shift value"); return -1; } // The expression must be evaluatable as an immediate. const MCConstantExpr *CE = dyn_cast(ShiftExpr); if (!CE) { Error(ImmLoc, "invalid immediate shift value"); return -1; } // Range check the immediate. // lsl, ror: 0 <= imm <= 31 // lsr, asr: 0 <= imm <= 32 Imm = CE->getValue(); if (Imm < 0 || ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { Error(ImmLoc, "immediate shift value out of range"); return -1; } // shift by zero is a nop. Always send it through as lsl. // ('as' compatibility) if (Imm == 0) ShiftTy = ARM_AM::lsl; } else if (Parser.getTok().is(AsmToken::Identifier)) { SMLoc L = Parser.getTok().getLoc(); EndLoc = Parser.getTok().getEndLoc(); ShiftReg = tryParseRegister(); if (ShiftReg == -1) { Error(L, "expected immediate or register in shift operand"); return -1; } } else { Error(Parser.getTok().getLoc(), "expected immediate or register in shift operand"); return -1; } } if (ShiftReg && ShiftTy != ARM_AM::rrx) Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, ShiftReg, Imm, S, EndLoc)); else Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, S, EndLoc)); return 0; } /// Try to parse a register name. The token must be an Identifier when called. /// If it's a register, an AsmOperand is created. Another AsmOperand is created /// if there is a "writeback". 'true' if it's not a register. /// /// TODO this is likely to change to allow different register types and or to /// parse for a specific register type. bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { const AsmToken &RegTok = Parser.getTok(); int RegNo = tryParseRegister(); if (RegNo == -1) return true; Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), RegTok.getEndLoc())); const AsmToken &ExclaimTok = Parser.getTok(); if (ExclaimTok.is(AsmToken::Exclaim)) { Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), ExclaimTok.getLoc())); Parser.Lex(); // Eat exclaim token return false; } // Also check for an index operand. This is only legal for vector registers, // but that'll get caught OK in operand matching, so we don't need to // explicitly filter everything else out here. if (Parser.getTok().is(AsmToken::LBrac)) { SMLoc SIdx = Parser.getTok().getLoc(); Parser.Lex(); // Eat left bracket token. const MCExpr *ImmVal; if (getParser().parseExpression(ImmVal)) return true; const MCConstantExpr *MCE = dyn_cast(ImmVal); if (!MCE) return TokError("immediate value expected for vector index"); if (Parser.getTok().isNot(AsmToken::RBrac)) return Error(Parser.getTok().getLoc(), "']' expected"); SMLoc E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat right bracket token. Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), SIdx, E, getContext())); } return false; } /// MatchCoprocessorOperandName - Try to parse an coprocessor related /// instruction with a symbolic operand name. /// We accept "crN" syntax for GAS compatibility. /// ::= /// If CoprocOp is 'c', then: /// ::= c | cr /// If CoprocOp is 'p', then : /// ::= p /// ::= integer in range [0, 15] static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { // Use the same layout as the tablegen'erated register name matcher. Ugly, // but efficient. if (Name.size() < 2 || Name[0] != CoprocOp) return -1; Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); switch (Name.size()) { default: return -1; case 1: switch (Name[0]) { default: return -1; case '0': return 0; case '1': return 1; case '2': return 2; case '3': return 3; case '4': return 4; case '5': return 5; case '6': return 6; case '7': return 7; case '8': return 8; case '9': return 9; } case 2: if (Name[0] != '1') return -1; switch (Name[1]) { default: return -1; // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON) case '0': return CoprocOp == 'p'? -1: 10; case '1': return CoprocOp == 'p'? -1: 11; case '2': return 12; case '3': return 13; case '4': return 14; case '5': return 15; } } } /// parseITCondCode - Try to parse a condition code for an IT instruction. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseITCondCode(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; unsigned CC = StringSwitch(Tok.getString().lower()) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) .Case("hs", ARMCC::HS) .Case("cs", ARMCC::HS) .Case("lo", ARMCC::LO) .Case("cc", ARMCC::LO) .Case("mi", ARMCC::MI) .Case("pl", ARMCC::PL) .Case("vs", ARMCC::VS) .Case("vc", ARMCC::VC) .Case("hi", ARMCC::HI) .Case("ls", ARMCC::LS) .Case("ge", ARMCC::GE) .Case("lt", ARMCC::LT) .Case("gt", ARMCC::GT) .Case("le", ARMCC::LE) .Case("al", ARMCC::AL) .Default(~0U); if (CC == ~0U) return MatchOperand_NoMatch; Parser.Lex(); // Eat the token. Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); return MatchOperand_Success; } /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); if (Num == -1) return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); return MatchOperand_Success; } /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); if (Reg == -1) return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); return MatchOperand_Success; } /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. /// coproc_option : '{' imm0_255 '}' ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); // If this isn't a '{', this isn't a coprocessor immediate operand. if (Parser.getTok().isNot(AsmToken::LCurly)) return MatchOperand_NoMatch; Parser.Lex(); // Eat the '{' const MCExpr *Expr; SMLoc Loc = Parser.getTok().getLoc(); if (getParser().parseExpression(Expr)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(Expr); if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); return MatchOperand_ParseFail; } int Val = CE->getValue(); // Check for and consume the closing '}' if (Parser.getTok().isNot(AsmToken::RCurly)) return MatchOperand_ParseFail; SMLoc E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat the '}' Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); return MatchOperand_Success; } // For register list parsing, we need to map from raw GPR register numbering // to the enumeration values. The enumeration values aren't sorted by // register number due to our using "sp", "lr" and "pc" as canonical names. static unsigned getNextRegister(unsigned Reg) { // If this is a GPR, we need to do it manually, otherwise we can rely // on the sort ordering of the enumeration since the other reg-classes // are sane. if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) return Reg + 1; switch(Reg) { default: llvm_unreachable("Invalid GPR number!"); case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; } } // Return the low-subreg of a given Q register. static unsigned getDRegFromQReg(unsigned QReg) { switch (QReg) { default: llvm_unreachable("expected a Q register!"); case ARM::Q0: return ARM::D0; case ARM::Q1: return ARM::D2; case ARM::Q2: return ARM::D4; case ARM::Q3: return ARM::D6; case ARM::Q4: return ARM::D8; case ARM::Q5: return ARM::D10; case ARM::Q6: return ARM::D12; case ARM::Q7: return ARM::D14; case ARM::Q8: return ARM::D16; case ARM::Q9: return ARM::D18; case ARM::Q10: return ARM::D20; case ARM::Q11: return ARM::D22; case ARM::Q12: return ARM::D24; case ARM::Q13: return ARM::D26; case ARM::Q14: return ARM::D28; case ARM::Q15: return ARM::D30; } } /// Parse a register list. bool ARMAsmParser::parseRegisterList(OperandVector &Operands) { assert(Parser.getTok().is(AsmToken::LCurly) && "Token is not a Left Curly Brace"); SMLoc S = Parser.getTok().getLoc(); Parser.Lex(); // Eat '{' token. SMLoc RegLoc = Parser.getTok().getLoc(); // Check the first register in the list to see what register class // this is a list of. int Reg = tryParseRegister(); if (Reg == -1) return Error(RegLoc, "register expected"); // The reglist instructions have at most 16 registers, so reserve // space for that many. int EReg = 0; SmallVector, 16> Registers; // Allow Q regs and just interpret them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { Reg = getDRegFromQReg(Reg); EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); ++Reg; } const MCRegisterClass *RC; if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; else return Error(RegLoc, "invalid register in register list"); // Store the register. EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); // This starts immediately after the first register token in the list, // so we can see either a comma or a minus (range separator) as a legal // next token. while (Parser.getTok().is(AsmToken::Comma) || Parser.getTok().is(AsmToken::Minus)) { if (Parser.getTok().is(AsmToken::Minus)) { Parser.Lex(); // Eat the minus. SMLoc AfterMinusLoc = Parser.getTok().getLoc(); int EndReg = tryParseRegister(); if (EndReg == -1) return Error(AfterMinusLoc, "register expected"); // Allow Q regs and just interpret them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) EndReg = getDRegFromQReg(EndReg) + 1; // If the register is the same as the start reg, there's nothing // more to do. if (Reg == EndReg) continue; // The register must be in the same register class as the first. if (!RC->contains(EndReg)) return Error(AfterMinusLoc, "invalid register in register list"); // Ranges must go from low to high. if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) return Error(AfterMinusLoc, "bad range in register list"); // Add all the registers in the range to the register list. while (Reg != EndReg) { Reg = getNextRegister(Reg); EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); } continue; } Parser.Lex(); // Eat the comma. RegLoc = Parser.getTok().getLoc(); int OldReg = Reg; const AsmToken RegTok = Parser.getTok(); Reg = tryParseRegister(); if (Reg == -1) return Error(RegLoc, "register expected"); // Allow Q regs and just interpret them as the two D sub-registers. bool isQReg = false; if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { Reg = getDRegFromQReg(Reg); isQReg = true; } // The register must be in the same register class as the first. if (!RC->contains(Reg)) return Error(RegLoc, "invalid register in register list"); // List must be monotonically increasing. if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) Warning(RegLoc, "register list not in ascending order"); else return Error(RegLoc, "register list not in ascending order"); } if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { Warning(RegLoc, "duplicated register (" + RegTok.getString() + ") in register list"); continue; } // VFP register lists must also be contiguous. if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && Reg != OldReg + 1) return Error(RegLoc, "non-contiguous register range"); EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); if (isQReg) { EReg = MRI->getEncodingValue(++Reg); Registers.push_back(std::pair(EReg, Reg)); } } if (Parser.getTok().isNot(AsmToken::RCurly)) return Error(Parser.getTok().getLoc(), "'}' expected"); SMLoc E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat '}' token. // Push the register list operand. Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); // The ARM system instruction variants for LDM/STM have a '^' token here. if (Parser.getTok().is(AsmToken::Caret)) { Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); Parser.Lex(); // Eat '^' token. } return false; } // Helper function to parse the lane index for vector lists. ARMAsmParser::OperandMatchResultTy ARMAsmParser:: parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { Index = 0; // Always return a defined index value. if (Parser.getTok().is(AsmToken::LBrac)) { Parser.Lex(); // Eat the '['. if (Parser.getTok().is(AsmToken::RBrac)) { // "Dn[]" is the 'all lanes' syntax. LaneKind = AllLanes; EndLoc = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat the ']'. return MatchOperand_Success; } // There's an optional '#' token here. Normally there wouldn't be, but // inline assemble puts one in, and it's friendly to accept that. if (Parser.getTok().is(AsmToken::Hash)) Parser.Lex(); // Eat '#' or '$'. const MCExpr *LaneIndex; SMLoc Loc = Parser.getTok().getLoc(); if (getParser().parseExpression(LaneIndex)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(LaneIndex); if (!CE) { Error(Loc, "lane index must be empty or an integer"); return MatchOperand_ParseFail; } if (Parser.getTok().isNot(AsmToken::RBrac)) { Error(Parser.getTok().getLoc(), "']' expected"); return MatchOperand_ParseFail; } EndLoc = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat the ']'. int64_t Val = CE->getValue(); // FIXME: Make this range check context sensitive for .8, .16, .32. if (Val < 0 || Val > 7) { Error(Parser.getTok().getLoc(), "lane index out of range"); return MatchOperand_ParseFail; } Index = Val; LaneKind = IndexedLane; return MatchOperand_Success; } LaneKind = NoLanes; return MatchOperand_Success; } // parse a vector register list ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseVectorList(OperandVector &Operands) { VectorLaneTy LaneKind; unsigned LaneIndex; SMLoc S = Parser.getTok().getLoc(); // As an extension (to match gas), support a plain D register or Q register // (without encosing curly braces) as a single or double entry list, // respectively. if (Parser.getTok().is(AsmToken::Identifier)) { SMLoc E = Parser.getTok().getEndLoc(); int Reg = tryParseRegister(); if (Reg == -1) return MatchOperand_NoMatch; if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); if (Res != MatchOperand_Success) return Res; switch (LaneKind) { case NoLanes: Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); break; case AllLanes: Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, LaneIndex, false, S, E)); break; } return MatchOperand_Success; } if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { Reg = getDRegFromQReg(Reg); OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); if (Res != MatchOperand_Success) return Res; switch (LaneKind) { case NoLanes: Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]); Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); break; case AllLanes: Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]); Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, LaneIndex, false, S, E)); break; } return MatchOperand_Success; } Error(S, "vector register expected"); return MatchOperand_ParseFail; } if (Parser.getTok().isNot(AsmToken::LCurly)) return MatchOperand_NoMatch; Parser.Lex(); // Eat '{' token. SMLoc RegLoc = Parser.getTok().getLoc(); int Reg = tryParseRegister(); if (Reg == -1) { Error(RegLoc, "register expected"); return MatchOperand_ParseFail; } unsigned Count = 1; int Spacing = 0; unsigned FirstReg = Reg; // The list is of D registers, but we also allow Q regs and just interpret // them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { FirstReg = Reg = getDRegFromQReg(Reg); Spacing = 1; // double-spacing requires explicit D registers, otherwise // it's ambiguous with four-register single spaced. ++Reg; ++Count; } SMLoc E; if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; while (Parser.getTok().is(AsmToken::Comma) || Parser.getTok().is(AsmToken::Minus)) { if (Parser.getTok().is(AsmToken::Minus)) { if (!Spacing) Spacing = 1; // Register range implies a single spaced list. else if (Spacing == 2) { Error(Parser.getTok().getLoc(), "sequential registers in double spaced list"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat the minus. SMLoc AfterMinusLoc = Parser.getTok().getLoc(); int EndReg = tryParseRegister(); if (EndReg == -1) { Error(AfterMinusLoc, "register expected"); return MatchOperand_ParseFail; } // Allow Q regs and just interpret them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) EndReg = getDRegFromQReg(EndReg) + 1; // If the register is the same as the start reg, there's nothing // more to do. if (Reg == EndReg) continue; // The register must be in the same register class as the first. if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { Error(AfterMinusLoc, "invalid register in register list"); return MatchOperand_ParseFail; } // Ranges must go from low to high. if (Reg > EndReg) { Error(AfterMinusLoc, "bad range in register list"); return MatchOperand_ParseFail; } // Parse the lane specifier if present. VectorLaneTy NextLaneKind; unsigned NextLaneIndex; if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { Error(AfterMinusLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } // Add all the registers in the range to the register list. Count += EndReg - Reg; Reg = EndReg; continue; } Parser.Lex(); // Eat the comma. RegLoc = Parser.getTok().getLoc(); int OldReg = Reg; Reg = tryParseRegister(); if (Reg == -1) { Error(RegLoc, "register expected"); return MatchOperand_ParseFail; } // vector register lists must be contiguous. // It's OK to use the enumeration values directly here rather, as the // VFP register classes have the enum sorted properly. // // The list is of D registers, but we also allow Q regs and just interpret // them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { if (!Spacing) Spacing = 1; // Register range implies a single spaced list. else if (Spacing == 2) { Error(RegLoc, "invalid register in double-spaced list (must be 'D' register')"); return MatchOperand_ParseFail; } Reg = getDRegFromQReg(Reg); if (Reg != OldReg + 1) { Error(RegLoc, "non-contiguous register range"); return MatchOperand_ParseFail; } ++Reg; Count += 2; // Parse the lane specifier if present. VectorLaneTy NextLaneKind; unsigned NextLaneIndex; SMLoc LaneLoc = Parser.getTok().getLoc(); if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { Error(LaneLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } continue; } // Normal D register. // Figure out the register spacing (single or double) of the list if // we don't know it already. if (!Spacing) Spacing = 1 + (Reg == OldReg + 2); // Just check that it's contiguous and keep going. if (Reg != OldReg + Spacing) { Error(RegLoc, "non-contiguous register range"); return MatchOperand_ParseFail; } ++Count; // Parse the lane specifier if present. VectorLaneTy NextLaneKind; unsigned NextLaneIndex; SMLoc EndLoc = Parser.getTok().getLoc(); if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { Error(EndLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } } if (Parser.getTok().isNot(AsmToken::RCurly)) { Error(Parser.getTok().getLoc(), "'}' expected"); return MatchOperand_ParseFail; } E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat '}' token. switch (LaneKind) { case NoLanes: // Two-register operands have been converted to the // composite register classes. if (Count == 2) { const MCRegisterClass *RC = (Spacing == 1) ? &ARMMCRegisterClasses[ARM::DPairRegClassID] : &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); } Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, (Spacing == 2), S, E)); break; case AllLanes: // Two-register operands have been converted to the // composite register classes. if (Count == 2) { const MCRegisterClass *RC = (Spacing == 1) ? &ARMMCRegisterClasses[ARM::DPairRegClassID] : &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); } Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, (Spacing == 2), S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, LaneIndex, (Spacing == 2), S, E)); break; } return MatchOperand_Success; } /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); unsigned Opt; if (Tok.is(AsmToken::Identifier)) { StringRef OptStr = Tok.getString(); Opt = StringSwitch(OptStr.slice(0, OptStr.size()).lower()) .Case("sy", ARM_MB::SY) .Case("st", ARM_MB::ST) .Case("ld", ARM_MB::LD) .Case("sh", ARM_MB::ISH) .Case("ish", ARM_MB::ISH) .Case("shst", ARM_MB::ISHST) .Case("ishst", ARM_MB::ISHST) .Case("ishld", ARM_MB::ISHLD) .Case("nsh", ARM_MB::NSH) .Case("un", ARM_MB::NSH) .Case("nshst", ARM_MB::NSHST) .Case("nshld", ARM_MB::NSHLD) .Case("unst", ARM_MB::NSHST) .Case("osh", ARM_MB::OSH) .Case("oshst", ARM_MB::OSHST) .Case("oshld", ARM_MB::OSHLD) .Default(~0U); // ishld, oshld, nshld and ld are only available from ARMv8. if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) Opt = ~0U; if (Opt == ~0U) return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. } else if (Tok.is(AsmToken::Hash) || Tok.is(AsmToken::Dollar) || Tok.is(AsmToken::Integer)) { if (Parser.getTok().isNot(AsmToken::Integer)) Parser.Lex(); // Eat '#' or '$'. SMLoc Loc = Parser.getTok().getLoc(); const MCExpr *MemBarrierID; if (getParser().parseExpression(MemBarrierID)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(MemBarrierID); if (!CE) { Error(Loc, "constant expression expected"); return MatchOperand_ParseFail; } int Val = CE->getValue(); if (Val & ~0xf) { Error(Loc, "immediate value out of range"); return MatchOperand_ParseFail; } Opt = ARM_MB::RESERVED_0 + Val; } else return MatchOperand_ParseFail; Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); return MatchOperand_Success; } /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); unsigned Opt; if (Tok.is(AsmToken::Identifier)) { StringRef OptStr = Tok.getString(); if (OptStr.equals_lower("sy")) Opt = ARM_ISB::SY; else return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. } else if (Tok.is(AsmToken::Hash) || Tok.is(AsmToken::Dollar) || Tok.is(AsmToken::Integer)) { if (Parser.getTok().isNot(AsmToken::Integer)) Parser.Lex(); // Eat '#' or '$'. SMLoc Loc = Parser.getTok().getLoc(); const MCExpr *ISBarrierID; if (getParser().parseExpression(ISBarrierID)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ISBarrierID); if (!CE) { Error(Loc, "constant expression expected"); return MatchOperand_ParseFail; } int Val = CE->getValue(); if (Val & ~0xf) { Error(Loc, "immediate value out of range"); return MatchOperand_ParseFail; } Opt = ARM_ISB::RESERVED_0 + Val; } else return MatchOperand_ParseFail; Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( (ARM_ISB::InstSyncBOpt)Opt, S)); return MatchOperand_Success; } /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; StringRef IFlagsStr = Tok.getString(); // An iflags string of "none" is interpreted to mean that none of the AIF // bits are set. Not a terribly useful instruction, but a valid encoding. unsigned IFlags = 0; if (IFlagsStr != "none") { for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { unsigned Flag = StringSwitch(IFlagsStr.substr(i, 1)) .Case("a", ARM_PROC::A) .Case("i", ARM_PROC::I) .Case("f", ARM_PROC::F) .Default(~0U); // If some specific iflag is already set, it means that some letter is // present more than once, this is not acceptable. if (Flag == ~0U || (IFlags & Flag)) return MatchOperand_NoMatch; IFlags |= Flag; } } Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); return MatchOperand_Success; } /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; StringRef Mask = Tok.getString(); if (isMClass()) { // See ARMv6-M 10.1.1 std::string Name = Mask.lower(); unsigned FlagsVal = StringSwitch(Name) // Note: in the documentation: // ARM deprecates using MSR APSR without a _ qualifier as an alias // for MSR APSR_nzcvq. // but we do make it an alias here. This is so to get the "mask encoding" // bits correct on MSR APSR writes. // // FIXME: Note the 0xc00 "mask encoding" bits version of the registers // should really only be allowed when writing a special register. Note // they get dropped in the MRS instruction reading a special register as // the SYSm field is only 8 bits. // // FIXME: the _g and _nzcvqg versions are only allowed if the processor // includes the DSP extension but that is not checked. .Case("apsr", 0x800) .Case("apsr_nzcvq", 0x800) .Case("apsr_g", 0x400) .Case("apsr_nzcvqg", 0xc00) .Case("iapsr", 0x801) .Case("iapsr_nzcvq", 0x801) .Case("iapsr_g", 0x401) .Case("iapsr_nzcvqg", 0xc01) .Case("eapsr", 0x802) .Case("eapsr_nzcvq", 0x802) .Case("eapsr_g", 0x402) .Case("eapsr_nzcvqg", 0xc02) .Case("xpsr", 0x803) .Case("xpsr_nzcvq", 0x803) .Case("xpsr_g", 0x403) .Case("xpsr_nzcvqg", 0xc03) .Case("ipsr", 0x805) .Case("epsr", 0x806) .Case("iepsr", 0x807) .Case("msp", 0x808) .Case("psp", 0x809) .Case("primask", 0x810) .Case("basepri", 0x811) .Case("basepri_max", 0x812) .Case("faultmask", 0x813) .Case("control", 0x814) .Default(~0U); if (FlagsVal == ~0U) return MatchOperand_NoMatch; if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) // basepri, basepri_max and faultmask only valid for V7m. return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); return MatchOperand_Success; } // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" size_t Start = 0, Next = Mask.find('_'); StringRef Flags = ""; std::string SpecReg = Mask.slice(Start, Next).lower(); if (Next != StringRef::npos) Flags = Mask.slice(Next+1, Mask.size()); // FlagsVal contains the complete mask: // 3-0: Mask // 4: Special Reg (cpsr, apsr => 0; spsr => 1) unsigned FlagsVal = 0; if (SpecReg == "apsr") { FlagsVal = StringSwitch(Flags) .Case("nzcvq", 0x8) // same as CPSR_f .Case("g", 0x4) // same as CPSR_s .Case("nzcvqg", 0xc) // same as CPSR_fs .Default(~0U); if (FlagsVal == ~0U) { if (!Flags.empty()) return MatchOperand_NoMatch; else FlagsVal = 8; // No flag } } else if (SpecReg == "cpsr" || SpecReg == "spsr") { // cpsr_all is an alias for cpsr_fc, as is plain cpsr. if (Flags == "all" || Flags == "") Flags = "fc"; for (int i = 0, e = Flags.size(); i != e; ++i) { unsigned Flag = StringSwitch(Flags.substr(i, 1)) .Case("c", 1) .Case("x", 2) .Case("s", 4) .Case("f", 8) .Default(~0U); // If some specific flag is already set, it means that some letter is // present more than once, this is not acceptable. if (FlagsVal == ~0U || (FlagsVal & Flag)) return MatchOperand_NoMatch; FlagsVal |= Flag; } } else // No match for special register. return MatchOperand_NoMatch; // Special register without flags is NOT equivalent to "fc" flags. // NOTE: This is a divergence from gas' behavior. Uncommenting the following // two lines would enable gas compatibility at the expense of breaking // round-tripping. // // if (!FlagsVal) // FlagsVal = 0x9; // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) if (SpecReg == "spsr") FlagsVal |= 16; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); return MatchOperand_Success; } ARMAsmParser::OperandMatchResultTy ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, int High) { const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) { Error(Parser.getTok().getLoc(), Op + " operand expected."); return MatchOperand_ParseFail; } StringRef ShiftName = Tok.getString(); std::string LowerOp = Op.lower(); std::string UpperOp = Op.upper(); if (ShiftName != LowerOp && ShiftName != UpperOp) { Error(Parser.getTok().getLoc(), Op + " operand expected."); return MatchOperand_ParseFail; } Parser.Lex(); // Eat shift type token. // There must be a '#' and a shift amount. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. const MCExpr *ShiftAmount; SMLoc Loc = Parser.getTok().getLoc(); SMLoc EndLoc; if (getParser().parseExpression(ShiftAmount, EndLoc)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ShiftAmount); if (!CE) { Error(Loc, "constant expression expected"); return MatchOperand_ParseFail; } int Val = CE->getValue(); if (Val < Low || Val > High) { Error(Loc, "immediate value out of range"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); return MatchOperand_Success; } ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseSetEndImm(OperandVector &Operands) { const AsmToken &Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); if (Tok.isNot(AsmToken::Identifier)) { Error(S, "'be' or 'le' operand expected"); return MatchOperand_ParseFail; } int Val = StringSwitch(Tok.getString().lower()) .Case("be", 1) .Case("le", 0) .Default(-1); Parser.Lex(); // Eat the token. if (Val == -1) { Error(S, "'be' or 'le' operand expected"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, Tok.getEndLoc())); return MatchOperand_Success; } /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT /// instructions. Legal values are: /// lsl #n 'n' in [0,31] /// asr #n 'n' in [1,32] /// n == 32 encoded as n == 0. ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseShifterImm(OperandVector &Operands) { const AsmToken &Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); if (Tok.isNot(AsmToken::Identifier)) { Error(S, "shift operator 'asr' or 'lsl' expected"); return MatchOperand_ParseFail; } StringRef ShiftName = Tok.getString(); bool isASR; if (ShiftName == "lsl" || ShiftName == "LSL") isASR = false; else if (ShiftName == "asr" || ShiftName == "ASR") isASR = true; else { Error(S, "shift operator 'asr' or 'lsl' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat the operator. // A '#' and a shift amount. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. SMLoc ExLoc = Parser.getTok().getLoc(); const MCExpr *ShiftAmount; SMLoc EndLoc; if (getParser().parseExpression(ShiftAmount, EndLoc)) { Error(ExLoc, "malformed shift expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ShiftAmount); if (!CE) { Error(ExLoc, "shift amount must be an immediate"); return MatchOperand_ParseFail; } int64_t Val = CE->getValue(); if (isASR) { // Shift amount must be in [1,32] if (Val < 1 || Val > 32) { Error(ExLoc, "'asr' shift amount must be in range [1,32]"); return MatchOperand_ParseFail; } // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. if (isThumb() && Val == 32) { Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); return MatchOperand_ParseFail; } if (Val == 32) Val = 0; } else { // Shift amount must be in [1,32] if (Val < 0 || Val > 31) { Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); return MatchOperand_ParseFail; } } Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); return MatchOperand_Success; } /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family /// of instructions. Legal values are: /// ror #n 'n' in {0, 8, 16, 24} ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseRotImm(OperandVector &Operands) { const AsmToken &Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; StringRef ShiftName = Tok.getString(); if (ShiftName != "ror" && ShiftName != "ROR") return MatchOperand_NoMatch; Parser.Lex(); // Eat the operator. // A '#' and a rotate amount. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. SMLoc ExLoc = Parser.getTok().getLoc(); const MCExpr *ShiftAmount; SMLoc EndLoc; if (getParser().parseExpression(ShiftAmount, EndLoc)) { Error(ExLoc, "malformed rotate expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ShiftAmount); if (!CE) { Error(ExLoc, "rotate amount must be an immediate"); return MatchOperand_ParseFail; } int64_t Val = CE->getValue(); // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) // normally, zero is represented in asm by omitting the rotate operand // entirely. if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); return MatchOperand_Success; } ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseBitfield(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); // The bitfield descriptor is really two operands, the LSB and the width. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. const MCExpr *LSBExpr; SMLoc E = Parser.getTok().getLoc(); if (getParser().parseExpression(LSBExpr)) { Error(E, "malformed immediate expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(LSBExpr); if (!CE) { Error(E, "'lsb' operand must be an immediate"); return MatchOperand_ParseFail; } int64_t LSB = CE->getValue(); // The LSB must be in the range [0,31] if (LSB < 0 || LSB > 31) { Error(E, "'lsb' operand must be in the range [0,31]"); return MatchOperand_ParseFail; } E = Parser.getTok().getLoc(); // Expect another immediate operand. if (Parser.getTok().isNot(AsmToken::Comma)) { Error(Parser.getTok().getLoc(), "too few operands"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. const MCExpr *WidthExpr; SMLoc EndLoc; if (getParser().parseExpression(WidthExpr, EndLoc)) { Error(E, "malformed immediate expression"); return MatchOperand_ParseFail; } CE = dyn_cast(WidthExpr); if (!CE) { Error(E, "'width' operand must be an immediate"); return MatchOperand_ParseFail; } int64_t Width = CE->getValue(); // The LSB must be in the range [1,32-lsb] if (Width < 1 || Width > 32 - LSB) { Error(E, "'width' operand must be in the range [1,32-lsb]"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); return MatchOperand_Success; } ARMAsmParser::OperandMatchResultTy ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { // Check for a post-index addressing register operand. Specifically: // postidx_reg := '+' register {, shift} // | '-' register {, shift} // | register {, shift} // This method must return MatchOperand_NoMatch without consuming any tokens // in the case where there is no match, as other alternatives take other // parse methods. AsmToken Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); bool haveEaten = false; bool isAdd = true; if (Tok.is(AsmToken::Plus)) { Parser.Lex(); // Eat the '+' token. haveEaten = true; } else if (Tok.is(AsmToken::Minus)) { Parser.Lex(); // Eat the '-' token. isAdd = false; haveEaten = true; } SMLoc E = Parser.getTok().getEndLoc(); int Reg = tryParseRegister(); if (Reg == -1) { if (!haveEaten) return MatchOperand_NoMatch; Error(Parser.getTok().getLoc(), "register expected"); return MatchOperand_ParseFail; } ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; unsigned ShiftImm = 0; if (Parser.getTok().is(AsmToken::Comma)) { Parser.Lex(); // Eat the ','. if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) return MatchOperand_ParseFail; // FIXME: Only approximates end...may include intervening whitespace. E = Parser.getTok().getLoc(); } Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, ShiftImm, S, E)); return MatchOperand_Success; } ARMAsmParser::OperandMatchResultTy ARMAsmParser::parseAM3Offset(OperandVector &Operands) { // Check for a post-index addressing register operand. Specifically: // am3offset := '+' register // | '-' register // | register // | # imm // | # + imm // | # - imm // This method must return MatchOperand_NoMatch without consuming any tokens // in the case where there is no match, as other alternatives take other // parse methods. AsmToken Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); // Do immediates first, as we always parse those if we have a '#'. if (Parser.getTok().is(AsmToken::Hash) || Parser.getTok().is(AsmToken::Dollar)) { Parser.Lex(); // Eat '#' or '$'. // Explicitly look for a '-', as we need to encode negative zero // differently. bool isNegative = Parser.getTok().is(AsmToken::Minus); const MCExpr *Offset; SMLoc E; if (getParser().parseExpression(Offset, E)) return MatchOperand_ParseFail; const MCConstantExpr *CE = dyn_cast(Offset); if (!CE) { Error(S, "constant expression expected"); return MatchOperand_ParseFail; } // Negative zero is encoded as the flag value INT32_MIN. int32_t Val = CE->getValue(); if (isNegative && Val == 0) Val = INT32_MIN; Operands.push_back( ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); return MatchOperand_Success; } bool haveEaten = false; bool isAdd = true; if (Tok.is(AsmToken::Plus)) { Parser.Lex(); // Eat the '+' token. haveEaten = true; } else if (Tok.is(AsmToken::Minus)) { Parser.Lex(); // Eat the '-' token. isAdd = false; haveEaten = true; } Tok = Parser.getTok(); int Reg = tryParseRegister(); if (Reg == -1) { if (!haveEaten) return MatchOperand_NoMatch; Error(Tok.getLoc(), "register expected"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 0, S, Tok.getEndLoc())); return MatchOperand_Success; } /// Convert parsed operands to MCInst. Needed here because this instruction /// only has two register operands, but multiplication is commutative so /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) { ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); // If we have a three-operand form, make sure to set Rn to be the operand // that isn't the same as Rd. unsigned RegOp = 4; if (Operands.size() == 6 && ((ARMOperand &)*Operands[4]).getReg() == ((ARMOperand &)*Operands[3]).getReg()) RegOp = 5; ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); Inst.addOperand(Inst.getOperand(0)); ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); } void ARMAsmParser::cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) { int CondOp = -1, ImmOp = -1; switch(Inst.getOpcode()) { case ARM::tB: case ARM::tBcc: CondOp = 1; ImmOp = 2; break; case ARM::t2B: case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); } // first decide whether or not the branch should be conditional // by looking at it's location relative to an IT block if(inITBlock()) { // inside an IT block we cannot have any conditional branches. any // such instructions needs to be converted to unconditional form switch(Inst.getOpcode()) { case ARM::tBcc: Inst.setOpcode(ARM::tB); break; case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; } } else { // outside IT blocks we can only have unconditional branches with AL // condition code or conditional branches with non-AL condition code unsigned Cond = static_cast(*Operands[CondOp]).getCondCode(); switch(Inst.getOpcode()) { case ARM::tB: case ARM::tBcc: Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); break; case ARM::t2B: case ARM::t2Bcc: Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); break; } } // now decide on encoding size based on branch target range switch(Inst.getOpcode()) { // classify tB as either t2B or t1B based on range of immediate operand case ARM::tB: { ARMOperand &op = static_cast(*Operands[ImmOp]); if (!op.isSignedOffset<11, 1>() && isThumbTwo()) Inst.setOpcode(ARM::t2B); break; } // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand case ARM::tBcc: { ARMOperand &op = static_cast(*Operands[ImmOp]); if (!op.isSignedOffset<8, 1>() && isThumbTwo()) Inst.setOpcode(ARM::t2Bcc); break; } } ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); } /// Parse an ARM memory expression, return false if successful else return true /// or an error. The first token must be a '[' when called. bool ARMAsmParser::parseMemory(OperandVector &Operands) { SMLoc S, E; assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a Left Bracket"); S = Parser.getTok().getLoc(); Parser.Lex(); // Eat left bracket token. const AsmToken &BaseRegTok = Parser.getTok(); int BaseRegNum = tryParseRegister(); if (BaseRegNum == -1) return Error(BaseRegTok.getLoc(), "register expected"); // The next token must either be a comma, a colon or a closing bracket. const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) return Error(Tok.getLoc(), "malformed memory operand"); if (Tok.is(AsmToken::RBrac)) { E = Tok.getEndLoc(); Parser.Lex(); // Eat right bracket token. Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, ARM_AM::no_shift, 0, 0, false, S, E)); // If there's a pre-indexing writeback marker, '!', just add it as a token // operand. It's rather odd, but syntactically valid. if (Parser.getTok().is(AsmToken::Exclaim)) { Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); Parser.Lex(); // Eat the '!'. } return false; } assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && "Lost colon or comma in memory operand?!"); if (Tok.is(AsmToken::Comma)) { Parser.Lex(); // Eat the comma. } // If we have a ':', it's an alignment specifier. if (Parser.getTok().is(AsmToken::Colon)) { Parser.Lex(); // Eat the ':'. E = Parser.getTok().getLoc(); SMLoc AlignmentLoc = Tok.getLoc(); const MCExpr *Expr; if (getParser().parseExpression(Expr)) return true; // The expression has to be a constant. Memory references with relocations // don't come through here, as they use the