//===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
// 
//                     The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
// 
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//

class PPCReg<string n> : Register<n> {
  let Namespace = "PPC";
}

// We identify all our registers with a 5-bit ID, for consistency's sake.

// GPR - One of the 32 32-bit general-purpose registers
class GPR<bits<5> num, string n> : PPCReg<n> {
  field bits<5> Num = num;
}

// GP8 - One of the 32 64-bit general-purpose registers
class GP8<GPR Alias> : PPCReg<Alias.Name> {
  field bits<5> Num = Alias.Num;
  let Aliases = [Alias];
}

// SPR - One of the 32-bit special-purpose registers
class SPR<bits<10> num, string n> : PPCReg<n> {
  field bits<10> Num = num;
}

// FPR - One of the 32 64-bit floating-point registers
class FPR<bits<5> num, string n> : PPCReg<n> {
  field bits<5> Num = num;
}

// VR - One of the 32 128-bit vector registers
class VR<bits<5> num, string n> : PPCReg<n> {
  field bits<5> Num = num;
}

// CR - One of the 8 4-bit condition registers
class CR<bits<5> num, string n> : PPCReg<n> {
  field bits<5> Num = num;
}

// General-purpose registers
def R0  : GPR< 0,  "r0">;  def R1  : GPR< 1,  "r1">;
def R2  : GPR< 2,  "r2">;  def R3  : GPR< 3,  "r3">;
def R4  : GPR< 4,  "r4">;  def R5  : GPR< 5,  "r5">;
def R6  : GPR< 6,  "r6">;  def R7  : GPR< 7,  "r7">;
def R8  : GPR< 8,  "r8">;  def R9  : GPR< 9,  "r9">;
def R10 : GPR<10, "r10">;  def R11 : GPR<11, "r11">;
def R12 : GPR<12, "r12">;  def R13 : GPR<13, "r13">;
def R14 : GPR<14, "r14">;  def R15 : GPR<15, "r15">;
def R16 : GPR<16, "r16">;  def R17 : GPR<17, "r17">;
def R18 : GPR<18, "r18">;  def R19 : GPR<19, "r19">;
def R20 : GPR<20, "r20">;  def R21 : GPR<21, "r21">;
def R22 : GPR<22, "r22">;  def R23 : GPR<23, "r23">;
def R24 : GPR<24, "r24">;  def R25 : GPR<25, "r25">;
def R26 : GPR<26, "r26">;  def R27 : GPR<27, "r27">;
def R28 : GPR<28, "r28">;  def R29 : GPR<29, "r29">;
def R30 : GPR<30, "r30">;  def R31 : GPR<31, "r31">;

// 64-bit General-purpose registers
def X0  : GP8< R0>;  def X1  : GP8< R1>;
def X2  : GP8< R2>;  def X3  : GP8< R3>;
def X4  : GP8< R4>;  def X5  : GP8< R5>;
def X6  : GP8< R6>;  def X7  : GP8< R7>;
def X8  : GP8< R8>;  def X9  : GP8< R9>;
def X10 : GP8<R10>;  def X11 : GP8<R11>;
def X12 : GP8<R12>;  def X13 : GP8<R13>;
def X14 : GP8<R14>;  def X15 : GP8<R15>;
def X16 : GP8<R16>;  def X17 : GP8<R17>;
def X18 : GP8<R18>;  def X19 : GP8<R19>;
def X20 : GP8<R20>;  def X21 : GP8<R21>;
def X22 : GP8<R22>;  def X23 : GP8<R23>;
def X24 : GP8<R24>;  def X25 : GP8<R25>;
def X26 : GP8<R26>;  def X27 : GP8<R27>;
def X28 : GP8<R28>;  def X29 : GP8<R29>;
def X30 : GP8<R30>;  def X31 : GP8<R31>;

// Floating-point registers
def F0  : FPR< 0,  "f0">;  def F1  : FPR< 1,  "f1">;
def F2  : FPR< 2,  "f2">;  def F3  : FPR< 3,  "f3">;
def F4  : FPR< 4,  "f4">;  def F5  : FPR< 5,  "f5">;
def F6  : FPR< 6,  "f6">;  def F7  : FPR< 7,  "f7">;
def F8  : FPR< 8,  "f8">;  def F9  : FPR< 9,  "f9">;
def F10 : FPR<10, "f10">;  def F11 : FPR<11, "f11">;
def F12 : FPR<12, "f12">;  def F13 : FPR<13, "f13">;
def F14 : FPR<14, "f14">;  def F15 : FPR<15, "f15">;
def F16 : FPR<16, "f16">;  def F17 : FPR<17, "f17">;
def F18 : FPR<18, "f18">;  def F19 : FPR<19, "f19">;
def F20 : FPR<20, "f20">;  def F21 : FPR<21, "f21">;
def F22 : FPR<22, "f22">;  def F23 : FPR<23, "f23">;
def F24 : FPR<24, "f24">;  def F25 : FPR<25, "f25">;
def F26 : FPR<26, "f26">;  def F27 : FPR<27, "f27">;
def F28 : FPR<28, "f28">;  def F29 : FPR<29, "f29">;
def F30 : FPR<30, "f30">;  def F31 : FPR<31, "f31">;

// Vector registers
def V0  : VR< 0,  "v0">;  def V1  : VR< 1,  "v1">;
def V2  : VR< 2,  "v2">;  def V3  : VR< 3,  "v3">;
def V4  : VR< 4,  "v4">;  def V5  : VR< 5,  "v5">;
def V6  : VR< 6,  "v6">;  def V7  : VR< 7,  "v7">;
def V8  : VR< 8,  "v8">;  def V9  : VR< 9,  "v9">;
def V10 : VR<10, "v10">;  def V11 : VR<11, "v11">;
def V12 : VR<12, "v12">;  def V13 : VR<13, "v13">;
def V14 : VR<14, "v14">;  def V15 : VR<15, "v15">;
def V16 : VR<16, "v16">;  def V17 : VR<17, "v17">;
def V18 : VR<18, "v18">;  def V19 : VR<19, "v19">;
def V20 : VR<20, "v20">;  def V21 : VR<21, "v21">;
def V22 : VR<22, "v22">;  def V23 : VR<23, "v23">;
def V24 : VR<24, "v24">;  def V25 : VR<25, "v25">;
def V26 : VR<26, "v26">;  def V27 : VR<27, "v27">;
def V28 : VR<28, "v28">;  def V29 : VR<29, "v29">;
def V30 : VR<30, "v30">;  def V31 : VR<31, "v31">;

// Condition registers
def CR0 : CR<0, "cr0">; def CR1 : CR<1, "cr1">;
def CR2 : CR<2, "cr2">; def CR3 : CR<3, "cr3">;
def CR4 : CR<4, "cr4">; def CR5 : CR<5, "cr5">;
def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">;

// Link register
def LR  : SPR<8, "lr">;
// Count register
def CTR : SPR<9, "ctr">;
// VRsave register
def VRSAVE: SPR<256, "VRsave">;

/// Register classes
// Allocate volatiles first
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
def GPRC : RegisterClass<"PPC", [i32], 32,
     [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
      R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
      R16, R15, R14, R13, R31, R0, R1, LR]>
{
  let MethodProtos = [{
    iterator allocation_order_begin(MachineFunction &MF) const;
    iterator allocation_order_end(MachineFunction &MF) const;
  }];
  let MethodBodies = [{
    GPRCClass::iterator
    GPRCClass::allocation_order_begin(MachineFunction &MF) const {
      return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
    }
    GPRCClass::iterator
    GPRCClass::allocation_order_end(MachineFunction &MF) const {
      if (hasFP(MF))
        return end()-4;  // don't allocate R31, R0, R1, LR
      else
        return end()-3;  // don't allocate R0, R1, LR
    }
  }];
}
def G8RC : RegisterClass<"PPC", [i64], 64,
     [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
      X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
      X16, X15, X14, X13, X31, X0, X1]>
{
  let MethodProtos = [{
    iterator allocation_order_begin(MachineFunction &MF) const;
    iterator allocation_order_end(MachineFunction &MF) const;
  }];
  let MethodBodies = [{
    G8RCClass::iterator
    G8RCClass::allocation_order_begin(MachineFunction &MF) const {
      return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
    }
    G8RCClass::iterator
    G8RCClass::allocation_order_end(MachineFunction &MF) const {
      if (hasFP(MF))
        return end()-3;
      else
        return end()-2;
    }
  }];
}



def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7,
  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
  F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
  F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;

def VRRC : RegisterClass<"PPC", [v16i8,v4f32,v4i32], 128,
 [V0, V1, V2, V3, V4, V5,
  V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
  V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;

def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 
  CR3, CR4]>;