mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
541d079947
Summary: Fix the cost of interleaved accesses for ARM/AArch64. We were calling getTypeAllocSize and using it to check the number of bits, when we should have called getTypeAllocSizeInBits instead. This would pottentially cause the vectorizer to generate loads/stores and shuffles which cannot be matched with an interleaved access instruction. No performance changes are expected for now since matching/generating interleaved accesses is still disabled by default. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11524 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243270 91177308-0d34-0410-b5e6-96231b3b80d8
506 lines
20 KiB
C++
506 lines
20 KiB
C++
//===-- ARMTargetTransformInfo.cpp - ARM specific TTI ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMTargetTransformInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "armtti"
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unsigned ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned Bits = Ty->getPrimitiveSizeInBits();
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if (Bits == 0 || Bits > 32)
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return 4;
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int32_t SImmVal = Imm.getSExtValue();
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uint32_t ZImmVal = Imm.getZExtValue();
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if (!ST->isThumb()) {
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if ((SImmVal >= 0 && SImmVal < 65536) ||
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(ARM_AM::getSOImmVal(ZImmVal) != -1) ||
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(ARM_AM::getSOImmVal(~ZImmVal) != -1))
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return 1;
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return ST->hasV6T2Ops() ? 2 : 3;
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}
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if (ST->isThumb2()) {
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if ((SImmVal >= 0 && SImmVal < 65536) ||
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(ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
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(ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
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return 1;
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return ST->hasV6T2Ops() ? 2 : 3;
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}
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// Thumb1.
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if (SImmVal >= 0 && SImmVal < 256)
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return 1;
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if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
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return 2;
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// Load from constantpool.
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return 3;
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}
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unsigned ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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// Single to/from double precision conversions.
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static const CostTblEntry<MVT::SimpleValueType> NEONFltDblTbl[] = {
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// Vector fptrunc/fpext conversions.
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{ ISD::FP_ROUND, MVT::v2f64, 2 },
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{ ISD::FP_EXTEND, MVT::v2f32, 2 },
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{ ISD::FP_EXTEND, MVT::v4f32, 4 }
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};
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if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
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ISD == ISD::FP_EXTEND)) {
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
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int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second);
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if (Idx != -1)
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return LT.first * NEONFltDblTbl[Idx].Cost;
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}
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EVT SrcTy = TLI->getValueType(DL, Src);
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EVT DstTy = TLI->getValueType(DL, Dst);
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if (!SrcTy.isSimple() || !DstTy.isSimple())
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return BaseT::getCastInstrCost(Opcode, Dst, Src);
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// Some arithmetic, load and store operations have specific instructions
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// to cast up/down their types automatically at no extra cost.
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// TODO: Get these tables to know at least what the related operations are.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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NEONVectorConversionTbl[] = {
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{ ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
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{ ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
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{ ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
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{ ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
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{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
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{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
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// The number of vmovl instructions for the extension.
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{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
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{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
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{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
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{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
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{ ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
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{ ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
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{ ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
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{ ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
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{ ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
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{ ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
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// Operations that we legalize using splitting.
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{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
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{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
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// Vector float <-> i32 conversions.
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
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{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
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{ ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
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{ ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
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{ ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
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{ ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
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{ ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
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{ ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
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// Vector double <-> i32 conversions.
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
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{ ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
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{ ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
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{ ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
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};
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if (SrcTy.isVector() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONVectorConversionTbl[Idx].Cost;
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}
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// Scalar float to integer conversions.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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NEONFloatConversionTbl[] = {
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{ ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
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{ ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
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{ ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
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{ ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
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{ ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
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{ ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
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{ ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
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{ ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
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};
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if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONFloatConversionTbl[Idx].Cost;
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}
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// Scalar integer to float conversions.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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NEONIntegerConversionTbl[] = {
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
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{ ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
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{ ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
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{ ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
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{ ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
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};
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if (SrcTy.isInteger() && ST->hasNEON()) {
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int Idx = ConvertCostTableLookup(NEONIntegerConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return NEONIntegerConversionTbl[Idx].Cost;
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}
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// Scalar integer conversion costs.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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ARMIntegerConversionTbl[] = {
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// i16 -> i64 requires two dependent operations.
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{ ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
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// Truncates on i64 are assumed to be free.
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{ ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
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{ ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
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};
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if (SrcTy.isInteger()) {
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int Idx = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
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DstTy.getSimpleVT(), SrcTy.getSimpleVT());
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if (Idx != -1)
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return ARMIntegerConversionTbl[Idx].Cost;
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}
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return BaseT::getCastInstrCost(Opcode, Dst, Src);
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}
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unsigned ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
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unsigned Index) {
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// Penalize inserting into an D-subregister. We end up with a three times
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// lower estimated throughput on swift.
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if (ST->isSwift() &&
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Opcode == Instruction::InsertElement &&
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ValTy->isVectorTy() &&
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ValTy->getScalarSizeInBits() <= 32)
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return 3;
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// Cross-class copies are expensive on many microarchitectures,
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// so assume they are expensive by default.
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if ((Opcode == Instruction::InsertElement ||
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Opcode == Instruction::ExtractElement) &&
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ValTy->getVectorElementType()->isIntegerTy())
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return 3;
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return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
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}
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unsigned ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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// On NEON a a vector select gets lowered to vbsl.
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if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
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// Lowering of some vector selects is currently far from perfect.
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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NEONVectorSelectTbl[] = {
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{ ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
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{ ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
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{ ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
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{ ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
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{ ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
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{ ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
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};
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EVT SelCondTy = TLI->getValueType(DL, CondTy);
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EVT SelValTy = TLI->getValueType(DL, ValTy);
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if (SelCondTy.isSimple() && SelValTy.isSimple()) {
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int Idx = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
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SelCondTy.getSimpleVT(),
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SelValTy.getSimpleVT());
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if (Idx != -1)
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return NEONVectorSelectTbl[Idx].Cost;
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}
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
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return LT.first;
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}
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return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
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}
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unsigned ARMTTIImpl::getAddressComputationCost(Type *Ty, bool IsComplex) {
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// Address computations in vectorized code with non-consecutive addresses will
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// likely result in more instructions compared to scalar code where the
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// computation can more often be merged into the index mode. The resulting
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// extra micro-ops can significantly decrease throughput.
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unsigned NumVectorInstToHideOverhead = 10;
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if (Ty->isVectorTy() && IsComplex)
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return NumVectorInstToHideOverhead;
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// In many cases the address computation is not merged into the instruction
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// addressing mode.
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return 1;
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}
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unsigned ARMTTIImpl::getFPOpCost(Type *Ty) {
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// Use similar logic that's in ARMISelLowering:
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// Any ARM CPU with VFP2 has floating point, but Thumb1 didn't have access
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// to VFP.
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if (ST->hasVFP2() && !ST->isThumb1Only()) {
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if (Ty->isFloatTy()) {
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return TargetTransformInfo::TCC_Basic;
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}
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if (Ty->isDoubleTy()) {
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return ST->isFPOnlySP() ? TargetTransformInfo::TCC_Expensive :
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TargetTransformInfo::TCC_Basic;
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}
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}
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return TargetTransformInfo::TCC_Expensive;
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}
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unsigned ARMTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) {
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// We only handle costs of reverse and alternate shuffles for now.
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if (Kind != TTI::SK_Reverse && Kind != TTI::SK_Alternate)
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return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
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if (Kind == TTI::SK_Reverse) {
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static const CostTblEntry<MVT::SimpleValueType> NEONShuffleTbl[] = {
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// Reverse shuffle cost one instruction if we are shuffling within a
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// double word (vrev) or two if we shuffle a quad word (vrev, vext).
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{ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
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{ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
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{ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
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|
{ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v8i16, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}};
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
|
|
|
|
int Idx = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
|
|
if (Idx == -1)
|
|
return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
|
|
return LT.first * NEONShuffleTbl[Idx].Cost;
|
|
}
|
|
if (Kind == TTI::SK_Alternate) {
|
|
static const CostTblEntry<MVT::SimpleValueType> NEONAltShuffleTbl[] = {
|
|
// Alt shuffle cost table for ARM. Cost is the number of instructions
|
|
// required to create the shuffled vector.
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v2i32, 1},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
|
|
{ISD::VECTOR_SHUFFLE, MVT::v4i16, 2},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v8i16, 16},
|
|
|
|
{ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}};
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
|
|
int Idx =
|
|
CostTableLookup(NEONAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
|
|
if (Idx == -1)
|
|
return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
return LT.first * NEONAltShuffleTbl[Idx].Cost;
|
|
}
|
|
return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
}
|
|
|
|
unsigned ARMTTIImpl::getArithmeticInstrCost(
|
|
unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
|
|
TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
|
|
TTI::OperandValueProperties Opd2PropInfo) {
|
|
|
|
int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
|
|
|
|
const unsigned FunctionCallDivCost = 20;
|
|
const unsigned ReciprocalDivCost = 10;
|
|
static const CostTblEntry<MVT::SimpleValueType> CostTbl[] = {
|
|
// Division.
|
|
// These costs are somewhat random. Choose a cost of 20 to indicate that
|
|
// vectorizing devision (added function call) is going to be very expensive.
|
|
// Double registers types.
|
|
{ ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
|
|
{ ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
|
|
{ ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
|
|
{ ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
|
|
{ ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
|
|
// Quad register types.
|
|
{ ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
|
|
{ ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
{ ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
{ ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
{ ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
|
// Multiplication.
|
|
};
|
|
|
|
int Idx = -1;
|
|
|
|
if (ST->hasNEON())
|
|
Idx = CostTableLookup(CostTbl, ISDOpcode, LT.second);
|
|
|
|
if (Idx != -1)
|
|
return LT.first * CostTbl[Idx].Cost;
|
|
|
|
unsigned Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
|
|
Opd1PropInfo, Opd2PropInfo);
|
|
|
|
// This is somewhat of a hack. The problem that we are facing is that SROA
|
|
// creates a sequence of shift, and, or instructions to construct values.
|
|
// These sequences are recognized by the ISel and have zero-cost. Not so for
|
|
// the vectorized code. Because we have support for v2i64 but not i64 those
|
|
// sequences look particularly beneficial to vectorize.
|
|
// To work around this we increase the cost of v2i64 operations to make them
|
|
// seem less beneficial.
|
|
if (LT.second == MVT::v2i64 &&
|
|
Op2Info == TargetTransformInfo::OK_UniformConstantValue)
|
|
Cost += 4;
|
|
|
|
return Cost;
|
|
}
|
|
|
|
unsigned ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
|
|
unsigned Alignment,
|
|
unsigned AddressSpace) {
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
|
|
|
|
if (Src->isVectorTy() && Alignment != 16 &&
|
|
Src->getVectorElementType()->isDoubleTy()) {
|
|
// Unaligned loads/stores are extremely inefficient.
|
|
// We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.
|
|
return LT.first * 4;
|
|
}
|
|
return LT.first;
|
|
}
|
|
|
|
unsigned ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
|
|
unsigned Factor,
|
|
ArrayRef<unsigned> Indices,
|
|
unsigned Alignment,
|
|
unsigned AddressSpace) {
|
|
assert(Factor >= 2 && "Invalid interleave factor");
|
|
assert(isa<VectorType>(VecTy) && "Expect a vector type");
|
|
|
|
// vldN/vstN doesn't support vector types of i64/f64 element.
|
|
bool EltIs64Bits = DL.getTypeAllocSizeInBits(VecTy->getScalarType()) == 64;
|
|
|
|
if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits) {
|
|
unsigned NumElts = VecTy->getVectorNumElements();
|
|
Type *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
|
|
unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
|
|
|
|
// vldN/vstN only support legal vector types of size 64 or 128 in bits.
|
|
if (NumElts % Factor == 0 && (SubVecSize == 64 || SubVecSize == 128))
|
|
return Factor;
|
|
}
|
|
|
|
return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
|
|
Alignment, AddressSpace);
|
|
}
|