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cd52a7a381
Apparently, the style needs to be agreed upon first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240390 91177308-0d34-0410-b5e6-96231b3b80d8
1008 lines
37 KiB
C++
1008 lines
37 KiB
C++
//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/LEB128.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include <array>
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#include <vector>
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using namespace llvm;
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using namespace Hexagon;
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#define DEBUG_TYPE "hexagon-disassembler"
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// Pull DecodeStatus and its enum values into the global namespace.
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typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// \brief Hexagon disassembler for all Hexagon platforms.
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class HexagonDisassembler : public MCDisassembler {
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public:
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std::unique_ptr<MCInst *> CurrentBundle;
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HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx), CurrentBundle(new MCInst *) {}
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DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream, raw_ostream &CStream,
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bool &Complete) const;
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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}
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static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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void const *Decoder);
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static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
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raw_ostream &os);
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static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst);
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static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static const uint16_t IntRegDecoderTable[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
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Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
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Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
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Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
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Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
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Hexagon::R30, Hexagon::R31};
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static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
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Hexagon::P2, Hexagon::P3};
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static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
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const uint16_t Table[], size_t Size) {
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if (RegNo < Size) {
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Inst.addOperand(MCOperand::createReg(Table[RegNo]));
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return MCDisassembler::Success;
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} else
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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void const *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Register = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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const void *Decoder) {
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static const uint16_t CtrlRegDecoderTable[] = {
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Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
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Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
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Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
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Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH};
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if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))
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return MCDisassembler::Fail;
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if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
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return MCDisassembler::Fail;
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unsigned Register = CtrlRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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void const *Decoder) {
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static const uint16_t CtrlReg64DecoderTable[] = {
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Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2,
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Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister,
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Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8,
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Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister,
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Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC,
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Hexagon::NoRegister};
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if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))
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return MCDisassembler::Fail;
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if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
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return MCDisassembler::Fail;
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unsigned Register = CtrlReg64DecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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const void *Decoder) {
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unsigned Register = 0;
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switch (RegNo) {
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case 0:
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Register = Hexagon::M0;
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break;
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case 1:
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Register = Hexagon::M1;
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break;
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default:
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return MCDisassembler::Fail;
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}
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Inst.addOperand(MCOperand::createReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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const void *Decoder) {
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static const uint16_t DoubleRegDecoderTable[] = {
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Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
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Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
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Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
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Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
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return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable,
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sizeof(DoubleRegDecoderTable)));
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}
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static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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void const *Decoder) {
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if (RegNo > 3)
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return MCDisassembler::Fail;
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unsigned Register = PredRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Register));
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return MCDisassembler::Success;
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}
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#include "HexagonGenDisassemblerTables.inc"
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static MCDisassembler *createHexagonDisassembler(Target const &T,
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MCSubtargetInfo const &STI,
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MCContext &Ctx) {
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return new HexagonDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeHexagonDisassembler() {
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TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
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createHexagonDisassembler);
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}
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DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &os,
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raw_ostream &cs) const {
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DecodeStatus Result = DecodeStatus::Success;
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bool Complete = false;
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Size = 0;
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*CurrentBundle = &MI;
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MI.setOpcode(Hexagon::BUNDLE);
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MI.addOperand(MCOperand::createImm(0));
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while (Result == Success && Complete == false) {
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if (Bytes.size() < HEXAGON_INSTR_SIZE)
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return MCDisassembler::Fail;
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MCInst *Inst = new (getContext()) MCInst;
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Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
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MI.addOperand(MCOperand::createInst(Inst));
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Size += HEXAGON_INSTR_SIZE;
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Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
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}
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return Result;
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}
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DecodeStatus HexagonDisassembler::getSingleInstruction(
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MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &os, raw_ostream &cs, bool &Complete) const {
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assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
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uint32_t Instruction =
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llvm::support::endian::read<uint32_t, llvm::support::little,
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llvm::support::unaligned>(Bytes.data());
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auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_LOOP_END) {
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if (BundleSize == 0)
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HexagonMCInstrInfo::setInnerLoop(MCB);
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else if (BundleSize == 1)
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HexagonMCInstrInfo::setOuterLoop(MCB);
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else
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return DecodeStatus::Fail;
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}
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DecodeStatus Result = DecodeStatus::Success;
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_DUPLEX) {
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// Determine the instruction class of each instruction in the duplex.
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unsigned duplexIClass, IClassLow, IClassHigh;
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duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
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switch (duplexIClass) {
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default:
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return MCDisassembler::Fail;
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case 0:
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IClassLow = HexagonII::HSIG_L1;
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IClassHigh = HexagonII::HSIG_L1;
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break;
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case 1:
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IClassLow = HexagonII::HSIG_L2;
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IClassHigh = HexagonII::HSIG_L1;
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break;
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case 2:
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IClassLow = HexagonII::HSIG_L2;
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IClassHigh = HexagonII::HSIG_L2;
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break;
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case 3:
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IClassLow = HexagonII::HSIG_A;
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IClassHigh = HexagonII::HSIG_A;
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break;
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case 4:
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IClassLow = HexagonII::HSIG_L1;
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IClassHigh = HexagonII::HSIG_A;
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break;
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case 5:
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IClassLow = HexagonII::HSIG_L2;
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IClassHigh = HexagonII::HSIG_A;
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break;
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case 6:
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IClassLow = HexagonII::HSIG_S1;
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IClassHigh = HexagonII::HSIG_A;
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break;
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case 7:
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IClassLow = HexagonII::HSIG_S2;
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IClassHigh = HexagonII::HSIG_A;
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break;
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case 8:
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IClassLow = HexagonII::HSIG_S1;
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IClassHigh = HexagonII::HSIG_L1;
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break;
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case 9:
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IClassLow = HexagonII::HSIG_S1;
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IClassHigh = HexagonII::HSIG_L2;
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break;
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case 10:
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IClassLow = HexagonII::HSIG_S1;
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IClassHigh = HexagonII::HSIG_S1;
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break;
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case 11:
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IClassLow = HexagonII::HSIG_S2;
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IClassHigh = HexagonII::HSIG_S1;
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break;
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case 12:
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IClassLow = HexagonII::HSIG_S2;
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IClassHigh = HexagonII::HSIG_L1;
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break;
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case 13:
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IClassLow = HexagonII::HSIG_S2;
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IClassHigh = HexagonII::HSIG_L2;
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break;
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case 14:
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IClassLow = HexagonII::HSIG_S2;
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IClassHigh = HexagonII::HSIG_S2;
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break;
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}
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// Set the MCInst to be a duplex instruction. Which one doesn't matter.
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MI.setOpcode(Hexagon::DuplexIClass0);
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// Decode each instruction in the duplex.
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// Create an MCInst for each instruction.
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unsigned instLow = Instruction & 0x1fff;
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unsigned instHigh = (Instruction >> 16) & 0x1fff;
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unsigned opLow;
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if (GetSubinstOpcode(IClassLow, instLow, opLow, os) !=
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MCDisassembler::Success)
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return MCDisassembler::Fail;
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unsigned opHigh;
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if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) !=
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MCDisassembler::Success)
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return MCDisassembler::Fail;
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MCInst *MILow = new (getContext()) MCInst;
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MILow->setOpcode(opLow);
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MCInst *MIHigh = new (getContext()) MCInst;
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MIHigh->setOpcode(opHigh);
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AddSubinstOperands(MILow, opLow, instLow);
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AddSubinstOperands(MIHigh, opHigh, instHigh);
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// see ConvertToSubInst() in
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// lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
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// Add the duplex instruction MCInsts as operands to the passed in MCInst.
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MCOperand OPLow = MCOperand::createInst(MILow);
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MCOperand OPHigh = MCOperand::createInst(MIHigh);
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MI.addOperand(OPLow);
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MI.addOperand(OPHigh);
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Complete = true;
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} else {
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_PACKET_END)
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Complete = true;
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// Calling the auto-generated decoder function.
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Result =
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decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
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}
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return Result;
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}
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static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<16>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<12>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<11>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<12>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<13>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<14>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<10>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,
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const void *Decoder) {
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uint64_t imm = SignExtend64<8>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<6>(tmp);
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|
MI.addOperand(MCOperand::createImm(imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
|
|
uint64_t /*Address*/, const void *Decoder) {
|
|
uint64_t imm = SignExtend64<4>(tmp);
|
|
MI.addOperand(MCOperand::createImm(imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
|
|
uint64_t /*Address*/, const void *Decoder) {
|
|
uint64_t imm = SignExtend64<5>(tmp);
|
|
MI.addOperand(MCOperand::createImm(imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
|
|
uint64_t /*Address*/, const void *Decoder) {
|
|
uint64_t imm = SignExtend64<6>(tmp);
|
|
MI.addOperand(MCOperand::createImm(imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
|
|
uint64_t /*Address*/, const void *Decoder) {
|
|
uint64_t imm = SignExtend64<7>(tmp);
|
|
MI.addOperand(MCOperand::createImm(imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
|
|
enum subInstBinaryValues {
|
|
V4_SA1_addi_BITS = 0x0000,
|
|
V4_SA1_addi_MASK = 0x1800,
|
|
V4_SA1_addrx_BITS = 0x1800,
|
|
V4_SA1_addrx_MASK = 0x1f00,
|
|
V4_SA1_addsp_BITS = 0x0c00,
|
|
V4_SA1_addsp_MASK = 0x1c00,
|
|
V4_SA1_and1_BITS = 0x1200,
|
|
V4_SA1_and1_MASK = 0x1f00,
|
|
V4_SA1_clrf_BITS = 0x1a70,
|
|
V4_SA1_clrf_MASK = 0x1e70,
|
|
V4_SA1_clrfnew_BITS = 0x1a50,
|
|
V4_SA1_clrfnew_MASK = 0x1e70,
|
|
V4_SA1_clrt_BITS = 0x1a60,
|
|
V4_SA1_clrt_MASK = 0x1e70,
|
|
V4_SA1_clrtnew_BITS = 0x1a40,
|
|
V4_SA1_clrtnew_MASK = 0x1e70,
|
|
V4_SA1_cmpeqi_BITS = 0x1900,
|
|
V4_SA1_cmpeqi_MASK = 0x1f00,
|
|
V4_SA1_combine0i_BITS = 0x1c00,
|
|
V4_SA1_combine0i_MASK = 0x1d18,
|
|
V4_SA1_combine1i_BITS = 0x1c08,
|
|
V4_SA1_combine1i_MASK = 0x1d18,
|
|
V4_SA1_combine2i_BITS = 0x1c10,
|
|
V4_SA1_combine2i_MASK = 0x1d18,
|
|
V4_SA1_combine3i_BITS = 0x1c18,
|
|
V4_SA1_combine3i_MASK = 0x1d18,
|
|
V4_SA1_combinerz_BITS = 0x1d08,
|
|
V4_SA1_combinerz_MASK = 0x1d08,
|
|
V4_SA1_combinezr_BITS = 0x1d00,
|
|
V4_SA1_combinezr_MASK = 0x1d08,
|
|
V4_SA1_dec_BITS = 0x1300,
|
|
V4_SA1_dec_MASK = 0x1f00,
|
|
V4_SA1_inc_BITS = 0x1100,
|
|
V4_SA1_inc_MASK = 0x1f00,
|
|
V4_SA1_seti_BITS = 0x0800,
|
|
V4_SA1_seti_MASK = 0x1c00,
|
|
V4_SA1_setin1_BITS = 0x1a00,
|
|
V4_SA1_setin1_MASK = 0x1e40,
|
|
V4_SA1_sxtb_BITS = 0x1500,
|
|
V4_SA1_sxtb_MASK = 0x1f00,
|
|
V4_SA1_sxth_BITS = 0x1400,
|
|
V4_SA1_sxth_MASK = 0x1f00,
|
|
V4_SA1_tfr_BITS = 0x1000,
|
|
V4_SA1_tfr_MASK = 0x1f00,
|
|
V4_SA1_zxtb_BITS = 0x1700,
|
|
V4_SA1_zxtb_MASK = 0x1f00,
|
|
V4_SA1_zxth_BITS = 0x1600,
|
|
V4_SA1_zxth_MASK = 0x1f00,
|
|
V4_SL1_loadri_io_BITS = 0x0000,
|
|
V4_SL1_loadri_io_MASK = 0x1000,
|
|
V4_SL1_loadrub_io_BITS = 0x1000,
|
|
V4_SL1_loadrub_io_MASK = 0x1000,
|
|
V4_SL2_deallocframe_BITS = 0x1f00,
|
|
V4_SL2_deallocframe_MASK = 0x1fc0,
|
|
V4_SL2_jumpr31_BITS = 0x1fc0,
|
|
V4_SL2_jumpr31_MASK = 0x1fc4,
|
|
V4_SL2_jumpr31_f_BITS = 0x1fc5,
|
|
V4_SL2_jumpr31_f_MASK = 0x1fc7,
|
|
V4_SL2_jumpr31_fnew_BITS = 0x1fc7,
|
|
V4_SL2_jumpr31_fnew_MASK = 0x1fc7,
|
|
V4_SL2_jumpr31_t_BITS = 0x1fc4,
|
|
V4_SL2_jumpr31_t_MASK = 0x1fc7,
|
|
V4_SL2_jumpr31_tnew_BITS = 0x1fc6,
|
|
V4_SL2_jumpr31_tnew_MASK = 0x1fc7,
|
|
V4_SL2_loadrb_io_BITS = 0x1000,
|
|
V4_SL2_loadrb_io_MASK = 0x1800,
|
|
V4_SL2_loadrd_sp_BITS = 0x1e00,
|
|
V4_SL2_loadrd_sp_MASK = 0x1f00,
|
|
V4_SL2_loadrh_io_BITS = 0x0000,
|
|
V4_SL2_loadrh_io_MASK = 0x1800,
|
|
V4_SL2_loadri_sp_BITS = 0x1c00,
|
|
V4_SL2_loadri_sp_MASK = 0x1e00,
|
|
V4_SL2_loadruh_io_BITS = 0x0800,
|
|
V4_SL2_loadruh_io_MASK = 0x1800,
|
|
V4_SL2_return_BITS = 0x1f40,
|
|
V4_SL2_return_MASK = 0x1fc4,
|
|
V4_SL2_return_f_BITS = 0x1f45,
|
|
V4_SL2_return_f_MASK = 0x1fc7,
|
|
V4_SL2_return_fnew_BITS = 0x1f47,
|
|
V4_SL2_return_fnew_MASK = 0x1fc7,
|
|
V4_SL2_return_t_BITS = 0x1f44,
|
|
V4_SL2_return_t_MASK = 0x1fc7,
|
|
V4_SL2_return_tnew_BITS = 0x1f46,
|
|
V4_SL2_return_tnew_MASK = 0x1fc7,
|
|
V4_SS1_storeb_io_BITS = 0x1000,
|
|
V4_SS1_storeb_io_MASK = 0x1000,
|
|
V4_SS1_storew_io_BITS = 0x0000,
|
|
V4_SS1_storew_io_MASK = 0x1000,
|
|
V4_SS2_allocframe_BITS = 0x1c00,
|
|
V4_SS2_allocframe_MASK = 0x1e00,
|
|
V4_SS2_storebi0_BITS = 0x1200,
|
|
V4_SS2_storebi0_MASK = 0x1f00,
|
|
V4_SS2_storebi1_BITS = 0x1300,
|
|
V4_SS2_storebi1_MASK = 0x1f00,
|
|
V4_SS2_stored_sp_BITS = 0x0a00,
|
|
V4_SS2_stored_sp_MASK = 0x1e00,
|
|
V4_SS2_storeh_io_BITS = 0x0000,
|
|
V4_SS2_storeh_io_MASK = 0x1800,
|
|
V4_SS2_storew_sp_BITS = 0x0800,
|
|
V4_SS2_storew_sp_MASK = 0x1e00,
|
|
V4_SS2_storewi0_BITS = 0x1000,
|
|
V4_SS2_storewi0_MASK = 0x1f00,
|
|
V4_SS2_storewi1_BITS = 0x1100,
|
|
V4_SS2_storewi1_MASK = 0x1f00
|
|
};
|
|
|
|
static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
|
|
raw_ostream &os) {
|
|
switch (IClass) {
|
|
case HexagonII::HSIG_L1:
|
|
if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS)
|
|
op = Hexagon::V4_SL1_loadri_io;
|
|
else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
|
|
op = Hexagon::V4_SL1_loadrub_io;
|
|
else {
|
|
os << "<unknown subinstruction>";
|
|
return MCDisassembler::Fail;
|
|
}
|
|
break;
|
|
case HexagonII::HSIG_L2:
|
|
if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS)
|
|
op = Hexagon::V4_SL2_deallocframe;
|
|
else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
|
|
op = Hexagon::V4_SL2_jumpr31;
|
|
else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
|
|
op = Hexagon::V4_SL2_jumpr31_f;
|
|
else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS)
|
|
op = Hexagon::V4_SL2_jumpr31_fnew;
|
|
else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS)
|
|
op = Hexagon::V4_SL2_jumpr31_t;
|
|
else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS)
|
|
op = Hexagon::V4_SL2_jumpr31_tnew;
|
|
else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS)
|
|
op = Hexagon::V4_SL2_loadrb_io;
|
|
else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS)
|
|
op = Hexagon::V4_SL2_loadrd_sp;
|
|
else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS)
|
|
op = Hexagon::V4_SL2_loadrh_io;
|
|
else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS)
|
|
op = Hexagon::V4_SL2_loadri_sp;
|
|
else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS)
|
|
op = Hexagon::V4_SL2_loadruh_io;
|
|
else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS)
|
|
op = Hexagon::V4_SL2_return;
|
|
else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS)
|
|
op = Hexagon::V4_SL2_return_f;
|
|
else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS)
|
|
op = Hexagon::V4_SL2_return_fnew;
|
|
else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS)
|
|
op = Hexagon::V4_SL2_return_t;
|
|
else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS)
|
|
op = Hexagon::V4_SL2_return_tnew;
|
|
else {
|
|
os << "<unknown subinstruction>";
|
|
return MCDisassembler::Fail;
|
|
}
|
|
break;
|
|
case HexagonII::HSIG_A:
|
|
if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS)
|
|
op = Hexagon::V4_SA1_addi;
|
|
else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS)
|
|
op = Hexagon::V4_SA1_addrx;
|
|
else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS)
|
|
op = Hexagon::V4_SA1_addsp;
|
|
else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS)
|
|
op = Hexagon::V4_SA1_and1;
|
|
else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS)
|
|
op = Hexagon::V4_SA1_clrf;
|
|
else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS)
|
|
op = Hexagon::V4_SA1_clrfnew;
|
|
else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS)
|
|
op = Hexagon::V4_SA1_clrt;
|
|
else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS)
|
|
op = Hexagon::V4_SA1_clrtnew;
|
|
else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS)
|
|
op = Hexagon::V4_SA1_cmpeqi;
|
|
else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS)
|
|
op = Hexagon::V4_SA1_combine0i;
|
|
else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS)
|
|
op = Hexagon::V4_SA1_combine1i;
|
|
else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS)
|
|
op = Hexagon::V4_SA1_combine2i;
|
|
else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS)
|
|
op = Hexagon::V4_SA1_combine3i;
|
|
else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS)
|
|
op = Hexagon::V4_SA1_combinerz;
|
|
else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS)
|
|
op = Hexagon::V4_SA1_combinezr;
|
|
else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS)
|
|
op = Hexagon::V4_SA1_dec;
|
|
else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS)
|
|
op = Hexagon::V4_SA1_inc;
|
|
else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS)
|
|
op = Hexagon::V4_SA1_seti;
|
|
else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS)
|
|
op = Hexagon::V4_SA1_setin1;
|
|
else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS)
|
|
op = Hexagon::V4_SA1_sxtb;
|
|
else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS)
|
|
op = Hexagon::V4_SA1_sxth;
|
|
else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS)
|
|
op = Hexagon::V4_SA1_tfr;
|
|
else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS)
|
|
op = Hexagon::V4_SA1_zxtb;
|
|
else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS)
|
|
op = Hexagon::V4_SA1_zxth;
|
|
else {
|
|
os << "<unknown subinstruction>";
|
|
return MCDisassembler::Fail;
|
|
}
|
|
break;
|
|
case HexagonII::HSIG_S1:
|
|
if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS)
|
|
op = Hexagon::V4_SS1_storeb_io;
|
|
else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS)
|
|
op = Hexagon::V4_SS1_storew_io;
|
|
else {
|
|
os << "<unknown subinstruction>";
|
|
return MCDisassembler::Fail;
|
|
}
|
|
break;
|
|
case HexagonII::HSIG_S2:
|
|
if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS)
|
|
op = Hexagon::V4_SS2_allocframe;
|
|
else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS)
|
|
op = Hexagon::V4_SS2_storebi0;
|
|
else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS)
|
|
op = Hexagon::V4_SS2_storebi1;
|
|
else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS)
|
|
op = Hexagon::V4_SS2_stored_sp;
|
|
else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS)
|
|
op = Hexagon::V4_SS2_storeh_io;
|
|
else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS)
|
|
op = Hexagon::V4_SS2_storew_sp;
|
|
else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS)
|
|
op = Hexagon::V4_SS2_storewi0;
|
|
else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS)
|
|
op = Hexagon::V4_SS2_storewi1;
|
|
else {
|
|
os << "<unknown subinstruction>";
|
|
return MCDisassembler::Fail;
|
|
}
|
|
break;
|
|
default:
|
|
os << "<unknown>";
|
|
return MCDisassembler::Fail;
|
|
}
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) {
|
|
if (encoded_reg < 8)
|
|
return Hexagon::R0 + encoded_reg;
|
|
else if (encoded_reg < 16)
|
|
return Hexagon::R0 + encoded_reg + 8;
|
|
return Hexagon::NoRegister;
|
|
}
|
|
|
|
static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) {
|
|
if (encoded_dreg < 4)
|
|
return Hexagon::D0 + encoded_dreg;
|
|
else if (encoded_dreg < 8)
|
|
return Hexagon::D0 + encoded_dreg + 4;
|
|
return Hexagon::NoRegister;
|
|
}
|
|
|
|
static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) {
|
|
int64_t operand;
|
|
MCOperand Op;
|
|
switch (opcode) {
|
|
case Hexagon::V4_SL2_deallocframe:
|
|
case Hexagon::V4_SL2_jumpr31:
|
|
case Hexagon::V4_SL2_jumpr31_f:
|
|
case Hexagon::V4_SL2_jumpr31_fnew:
|
|
case Hexagon::V4_SL2_jumpr31_t:
|
|
case Hexagon::V4_SL2_jumpr31_tnew:
|
|
case Hexagon::V4_SL2_return:
|
|
case Hexagon::V4_SL2_return_f:
|
|
case Hexagon::V4_SL2_return_fnew:
|
|
case Hexagon::V4_SL2_return_t:
|
|
case Hexagon::V4_SL2_return_tnew:
|
|
// no operands for these instructions
|
|
break;
|
|
case Hexagon::V4_SS2_allocframe:
|
|
// u 8-4{5_3}
|
|
operand = ((inst & 0x1f0) >> 4) << 3;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SL1_loadri_io:
|
|
// Rd 3-0, Rs 7-4, u 11-8{4_2}
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = (inst & 0xf00) >> 6;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SL1_loadrub_io:
|
|
// Rd 3-0, Rs 7-4, u 11-8
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = (inst & 0xf00) >> 8;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SL2_loadrb_io:
|
|
// Rd 3-0, Rs 7-4, u 10-8
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = (inst & 0x700) >> 8;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SL2_loadrh_io:
|
|
case Hexagon::V4_SL2_loadruh_io:
|
|
// Rd 3-0, Rs 7-4, u 10-8{3_1}
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = ((inst & 0x700) >> 8) << 1;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SL2_loadrd_sp:
|
|
// Rdd 2-0, u 7-3{5_3}
|
|
operand = getDRegFromSubinstEncoding(inst & 0x7);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = ((inst & 0x0f8) >> 3) << 3;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SL2_loadri_sp:
|
|
// Rd 3-0, u 8-4{5_2}
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = ((inst & 0x1f0) >> 4) << 2;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_addi:
|
|
// Rx 3-0 (x2), s7 10-4
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
MI->addOperand(Op);
|
|
operand = SignExtend64<7>((inst & 0x7f0) >> 4);
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_addrx:
|
|
// Rx 3-0 (x2), Rs 7-4
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
case Hexagon::V4_SA1_and1:
|
|
case Hexagon::V4_SA1_dec:
|
|
case Hexagon::V4_SA1_inc:
|
|
case Hexagon::V4_SA1_sxtb:
|
|
case Hexagon::V4_SA1_sxth:
|
|
case Hexagon::V4_SA1_tfr:
|
|
case Hexagon::V4_SA1_zxtb:
|
|
case Hexagon::V4_SA1_zxth:
|
|
// Rd 3-0, Rs 7-4
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_addsp:
|
|
// Rd 3-0, u 9-4{6_2}
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = ((inst & 0x3f0) >> 4) << 2;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_seti:
|
|
// Rd 3-0, u 9-4
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = (inst & 0x3f0) >> 4;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_clrf:
|
|
case Hexagon::V4_SA1_clrfnew:
|
|
case Hexagon::V4_SA1_clrt:
|
|
case Hexagon::V4_SA1_clrtnew:
|
|
case Hexagon::V4_SA1_setin1:
|
|
// Rd 3-0
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_cmpeqi:
|
|
// Rs 7-4, u 1-0
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = inst & 0x3;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_combine0i:
|
|
case Hexagon::V4_SA1_combine1i:
|
|
case Hexagon::V4_SA1_combine2i:
|
|
case Hexagon::V4_SA1_combine3i:
|
|
// Rdd 2-0, u 6-5
|
|
operand = getDRegFromSubinstEncoding(inst & 0x7);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = (inst & 0x060) >> 5;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SA1_combinerz:
|
|
case Hexagon::V4_SA1_combinezr:
|
|
// Rdd 2-0, Rs 7-4
|
|
operand = getDRegFromSubinstEncoding(inst & 0x7);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SS1_storeb_io:
|
|
// Rs 7-4, u 11-8, Rt 3-0
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = (inst & 0xf00) >> 8;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SS1_storew_io:
|
|
// Rs 7-4, u 11-8{4_2}, Rt 3-0
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = ((inst & 0xf00) >> 8) << 2;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SS2_storebi0:
|
|
case Hexagon::V4_SS2_storebi1:
|
|
// Rs 7-4, u 3-0
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = inst & 0xf;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SS2_storewi0:
|
|
case Hexagon::V4_SS2_storewi1:
|
|
// Rs 7-4, u 3-0{4_2}
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = (inst & 0xf) << 2;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SS2_stored_sp:
|
|
// s 8-3{6_3}, Rtt 2-0
|
|
operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
operand = getDRegFromSubinstEncoding(inst & 0x7);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
case Hexagon::V4_SS2_storeh_io:
|
|
// Rs 7-4, u 10-8{3_1}, Rt 3-0
|
|
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
operand = ((inst & 0x700) >> 8) << 1;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
case Hexagon::V4_SS2_storew_sp:
|
|
// u 8-4{5_2}, Rd 3-0
|
|
operand = ((inst & 0x1f0) >> 4) << 2;
|
|
Op = MCOperand::createImm(operand);
|
|
MI->addOperand(Op);
|
|
operand = getRegFromSubinstEncoding(inst & 0xf);
|
|
Op = MCOperand::createReg(operand);
|
|
MI->addOperand(Op);
|
|
break;
|
|
default:
|
|
// don't crash with an invalid subinstruction
|
|
// llvm_unreachable("Invalid subinstruction in duplex instruction");
|
|
break;
|
|
}
|
|
}
|