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https://github.com/c64scene-ar/llvm-6502.git
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cd52a7a381
Apparently, the style needs to be agreed upon first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240390 91177308-0d34-0410-b5e6-96231b3b80d8
252 lines
8.0 KiB
C++
252 lines
8.0 KiB
C++
//===-- HexagonELFObjectWriter.cpp - Hexagon Target Descriptions ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonFixupKinds.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "hexagon-elf-writer"
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using namespace llvm;
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using namespace Hexagon;
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namespace {
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class HexagonELFObjectWriter : public MCELFObjectTargetWriter {
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private:
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StringRef CPU;
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public:
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HexagonELFObjectWriter(uint8_t OSABI, StringRef C);
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unsigned GetRelocType(MCValue const &Target, MCFixup const &Fixup,
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bool IsPCRel) const override;
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};
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}
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HexagonELFObjectWriter::HexagonELFObjectWriter(uint8_t OSABI, StringRef C)
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: MCELFObjectTargetWriter(/*Is64bit*/ false, OSABI, ELF::EM_HEXAGON,
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/*HasRelocationAddend*/ true),
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CPU(C) {}
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unsigned HexagonELFObjectWriter::GetRelocType(MCValue const & /*Target*/,
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MCFixup const &Fixup,
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bool IsPCRel) const {
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switch ((unsigned)Fixup.getKind()) {
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default:
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DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
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llvm_unreachable("Unimplemented Fixup kind!");
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return ELF::R_HEX_NONE;
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case FK_Data_4:
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return (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
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case FK_PCRel_4:
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return ELF::R_HEX_32_PCREL;
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case FK_Data_2:
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return ELF::R_HEX_16;
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case FK_Data_1:
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return ELF::R_HEX_8;
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case fixup_Hexagon_B22_PCREL:
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return ELF::R_HEX_B22_PCREL;
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case fixup_Hexagon_B15_PCREL:
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return ELF::R_HEX_B15_PCREL;
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case fixup_Hexagon_B7_PCREL:
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return ELF::R_HEX_B7_PCREL;
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case fixup_Hexagon_LO16:
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return ELF::R_HEX_LO16;
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case fixup_Hexagon_HI16:
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return ELF::R_HEX_HI16;
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case fixup_Hexagon_32:
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return ELF::R_HEX_32;
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case fixup_Hexagon_16:
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return ELF::R_HEX_16;
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case fixup_Hexagon_8:
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return ELF::R_HEX_8;
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case fixup_Hexagon_GPREL16_0:
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return ELF::R_HEX_GPREL16_0;
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case fixup_Hexagon_GPREL16_1:
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return ELF::R_HEX_GPREL16_1;
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case fixup_Hexagon_GPREL16_2:
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return ELF::R_HEX_GPREL16_2;
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case fixup_Hexagon_GPREL16_3:
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return ELF::R_HEX_GPREL16_3;
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case fixup_Hexagon_HL16:
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return ELF::R_HEX_HL16;
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case fixup_Hexagon_B13_PCREL:
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return ELF::R_HEX_B13_PCREL;
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case fixup_Hexagon_B9_PCREL:
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return ELF::R_HEX_B9_PCREL;
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case fixup_Hexagon_B32_PCREL_X:
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return ELF::R_HEX_B32_PCREL_X;
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case fixup_Hexagon_32_6_X:
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return ELF::R_HEX_32_6_X;
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case fixup_Hexagon_B22_PCREL_X:
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return ELF::R_HEX_B22_PCREL_X;
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case fixup_Hexagon_B15_PCREL_X:
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return ELF::R_HEX_B15_PCREL_X;
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case fixup_Hexagon_B13_PCREL_X:
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return ELF::R_HEX_B13_PCREL_X;
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case fixup_Hexagon_B9_PCREL_X:
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return ELF::R_HEX_B9_PCREL_X;
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case fixup_Hexagon_B7_PCREL_X:
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return ELF::R_HEX_B7_PCREL_X;
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case fixup_Hexagon_16_X:
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return ELF::R_HEX_16_X;
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case fixup_Hexagon_12_X:
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return ELF::R_HEX_12_X;
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case fixup_Hexagon_11_X:
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return ELF::R_HEX_11_X;
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case fixup_Hexagon_10_X:
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return ELF::R_HEX_10_X;
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case fixup_Hexagon_9_X:
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return ELF::R_HEX_9_X;
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case fixup_Hexagon_8_X:
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return ELF::R_HEX_8_X;
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case fixup_Hexagon_7_X:
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return ELF::R_HEX_7_X;
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case fixup_Hexagon_6_X:
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return ELF::R_HEX_6_X;
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case fixup_Hexagon_32_PCREL:
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return ELF::R_HEX_32_PCREL;
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case fixup_Hexagon_COPY:
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return ELF::R_HEX_COPY;
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case fixup_Hexagon_GLOB_DAT:
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return ELF::R_HEX_GLOB_DAT;
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case fixup_Hexagon_JMP_SLOT:
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return ELF::R_HEX_JMP_SLOT;
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case fixup_Hexagon_RELATIVE:
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return ELF::R_HEX_RELATIVE;
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case fixup_Hexagon_PLT_B22_PCREL:
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return ELF::R_HEX_PLT_B22_PCREL;
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case fixup_Hexagon_GOTREL_LO16:
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return ELF::R_HEX_GOTREL_LO16;
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case fixup_Hexagon_GOTREL_HI16:
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return ELF::R_HEX_GOTREL_HI16;
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case fixup_Hexagon_GOTREL_32:
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return ELF::R_HEX_GOTREL_32;
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case fixup_Hexagon_GOT_LO16:
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return ELF::R_HEX_GOT_LO16;
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case fixup_Hexagon_GOT_HI16:
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return ELF::R_HEX_GOT_HI16;
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case fixup_Hexagon_GOT_32:
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return ELF::R_HEX_GOT_32;
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case fixup_Hexagon_GOT_16:
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return ELF::R_HEX_GOT_16;
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case fixup_Hexagon_DTPMOD_32:
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return ELF::R_HEX_DTPMOD_32;
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case fixup_Hexagon_DTPREL_LO16:
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return ELF::R_HEX_DTPREL_LO16;
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case fixup_Hexagon_DTPREL_HI16:
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return ELF::R_HEX_DTPREL_HI16;
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case fixup_Hexagon_DTPREL_32:
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return ELF::R_HEX_DTPREL_32;
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case fixup_Hexagon_DTPREL_16:
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return ELF::R_HEX_DTPREL_16;
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case fixup_Hexagon_GD_PLT_B22_PCREL:
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return ELF::R_HEX_GD_PLT_B22_PCREL;
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case fixup_Hexagon_LD_PLT_B22_PCREL:
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return ELF::R_HEX_LD_PLT_B22_PCREL;
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case fixup_Hexagon_GD_GOT_LO16:
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return ELF::R_HEX_GD_GOT_LO16;
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case fixup_Hexagon_GD_GOT_HI16:
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return ELF::R_HEX_GD_GOT_HI16;
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case fixup_Hexagon_GD_GOT_32:
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return ELF::R_HEX_GD_GOT_32;
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case fixup_Hexagon_GD_GOT_16:
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return ELF::R_HEX_GD_GOT_16;
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case fixup_Hexagon_LD_GOT_LO16:
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return ELF::R_HEX_LD_GOT_LO16;
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case fixup_Hexagon_LD_GOT_HI16:
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return ELF::R_HEX_LD_GOT_HI16;
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case fixup_Hexagon_LD_GOT_32:
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return ELF::R_HEX_LD_GOT_32;
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case fixup_Hexagon_LD_GOT_16:
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return ELF::R_HEX_LD_GOT_16;
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case fixup_Hexagon_IE_LO16:
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return ELF::R_HEX_IE_LO16;
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case fixup_Hexagon_IE_HI16:
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return ELF::R_HEX_IE_HI16;
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case fixup_Hexagon_IE_32:
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return ELF::R_HEX_IE_32;
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case fixup_Hexagon_IE_GOT_LO16:
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return ELF::R_HEX_IE_GOT_LO16;
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case fixup_Hexagon_IE_GOT_HI16:
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return ELF::R_HEX_IE_GOT_HI16;
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case fixup_Hexagon_IE_GOT_32:
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return ELF::R_HEX_IE_GOT_32;
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case fixup_Hexagon_IE_GOT_16:
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return ELF::R_HEX_IE_GOT_16;
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case fixup_Hexagon_TPREL_LO16:
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return ELF::R_HEX_TPREL_LO16;
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case fixup_Hexagon_TPREL_HI16:
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return ELF::R_HEX_TPREL_HI16;
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case fixup_Hexagon_TPREL_32:
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return ELF::R_HEX_TPREL_32;
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case fixup_Hexagon_TPREL_16:
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return ELF::R_HEX_TPREL_16;
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case fixup_Hexagon_6_PCREL_X:
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return ELF::R_HEX_6_PCREL_X;
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case fixup_Hexagon_GOTREL_32_6_X:
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return ELF::R_HEX_GOTREL_32_6_X;
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case fixup_Hexagon_GOTREL_16_X:
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return ELF::R_HEX_GOTREL_16_X;
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case fixup_Hexagon_GOTREL_11_X:
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return ELF::R_HEX_GOTREL_11_X;
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case fixup_Hexagon_GOT_32_6_X:
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return ELF::R_HEX_GOT_32_6_X;
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case fixup_Hexagon_GOT_16_X:
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return ELF::R_HEX_GOT_16_X;
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case fixup_Hexagon_GOT_11_X:
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return ELF::R_HEX_GOT_11_X;
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case fixup_Hexagon_DTPREL_32_6_X:
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return ELF::R_HEX_DTPREL_32_6_X;
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case fixup_Hexagon_DTPREL_16_X:
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return ELF::R_HEX_DTPREL_16_X;
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case fixup_Hexagon_DTPREL_11_X:
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return ELF::R_HEX_DTPREL_11_X;
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case fixup_Hexagon_GD_GOT_32_6_X:
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return ELF::R_HEX_GD_GOT_32_6_X;
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case fixup_Hexagon_GD_GOT_16_X:
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return ELF::R_HEX_GD_GOT_16_X;
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case fixup_Hexagon_GD_GOT_11_X:
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return ELF::R_HEX_GD_GOT_11_X;
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case fixup_Hexagon_LD_GOT_32_6_X:
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return ELF::R_HEX_LD_GOT_32_6_X;
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case fixup_Hexagon_LD_GOT_16_X:
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return ELF::R_HEX_LD_GOT_16_X;
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case fixup_Hexagon_LD_GOT_11_X:
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return ELF::R_HEX_LD_GOT_11_X;
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case fixup_Hexagon_IE_32_6_X:
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return ELF::R_HEX_IE_32_6_X;
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case fixup_Hexagon_IE_16_X:
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return ELF::R_HEX_IE_16_X;
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case fixup_Hexagon_IE_GOT_32_6_X:
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return ELF::R_HEX_IE_GOT_32_6_X;
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case fixup_Hexagon_IE_GOT_16_X:
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return ELF::R_HEX_IE_GOT_16_X;
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case fixup_Hexagon_IE_GOT_11_X:
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return ELF::R_HEX_IE_GOT_11_X;
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case fixup_Hexagon_TPREL_32_6_X:
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return ELF::R_HEX_TPREL_32_6_X;
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case fixup_Hexagon_TPREL_16_X:
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return ELF::R_HEX_TPREL_16_X;
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case fixup_Hexagon_TPREL_11_X:
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return ELF::R_HEX_TPREL_11_X;
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}
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}
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MCObjectWriter *llvm::createHexagonELFObjectWriter(raw_pwrite_stream &OS,
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uint8_t OSABI,
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StringRef CPU) {
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MCELFObjectTargetWriter *MOTW = new HexagonELFObjectWriter(OSABI, CPU);
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return createELFObjectWriter(MOTW, OS, /*IsLittleEndian*/ true);
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}
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