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2f7322b348
This patch introduces a new pass that computes the safe point to insert the prologue and epilogue of the function. The interest is to find safe points that are cheaper than the entry and exits blocks. As an example and to avoid regressions to be introduce, this patch also implements the required bits to enable the shrink-wrapping pass for AArch64. ** Context ** Currently we insert the prologue and epilogue of the method/function in the entry and exits blocks. Although this is correct, we can do a better job when those are not immediately required and insert them at less frequently executed places. The job of the shrink-wrapping pass is to identify such places. ** Motivating example ** Let us consider the following function that perform a call only in one branch of a if: define i32 @f(i32 %a, i32 %b) { %tmp = alloca i32, align 4 %tmp2 = icmp slt i32 %a, %b br i1 %tmp2, label %true, label %false true: store i32 %a, i32* %tmp, align 4 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp) br label %false false: %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ] ret i32 %tmp.0 } On AArch64 this code generates (removing the cfi directives to ease readabilities): _f: ; @f ; BB#0: stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething LBB0_2: ; %false mov sp, x29 ldp x29, x30, [sp], #16 ret With shrink-wrapping we could generate: _f: ; @f ; BB#0: cmp w0, w1 b.ge LBB0_2 ; BB#1: ; %true stp x29, x30, [sp, #-16]! mov x29, sp sub sp, sp, #16 ; =16 stur w0, [x29, #-4] sub x1, x29, #4 ; =4 mov w0, wzr bl _doSomething add sp, x29, #16 ; =16 ldp x29, x30, [sp], #16 LBB0_2: ; %false ret Therefore, we would pay the overhead of setting up/destroying the frame only if we actually do the call. ** Proposed Solution ** This patch introduces a new machine pass that perform the shrink-wrapping analysis (See the comments at the beginning of ShrinkWrap.cpp for more details). It then stores the safe save and restore point into the MachineFrameInfo attached to the MachineFunction. This information is then used by the PrologEpilogInserter (PEI) to place the related code at the right place. This pass runs right before the PEI. Unlike the original paper of Chow from PLDI’88, this implementation of shrink-wrapping does not use expensive data-flow analysis and does not need hack to properly avoid frequently executed point. Instead, it relies on dominance and loop properties. The pass is off by default and each target can opt-in by setting the EnableShrinkWrap boolean to true in their derived class of TargetPassConfig. This setting can also be overwritten on the command line by using -enable-shrink-wrap. Before you try out the pass for your target, make sure you properly fix your emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not necessarily the entry block. ** Design Decisions ** 1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but for debugging and clarity I thought it was best to have its own file. 2. Right now, we only support one save point and one restore point. At some point we can expand this to several save point and restore point, the impacted component would then be: - The pass itself: New algorithm needed. - MachineFrameInfo: Hold a list or set of Save/Restore point instead of one pointer. - PEI: Should loop over the save point and restore point. Anyhow, at least for this first iteration, I do not believe this is interesting to support the complex cases. We should revisit that when we motivating examples. Differential Revision: http://reviews.llvm.org/D9210 <rdar://problem/3201744> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236507 91177308-0d34-0410-b5e6-96231b3b80d8
300 lines
10 KiB
C++
300 lines
10 KiB
C++
//===-- MSP430FrameLowering.cpp - MSP430 Frame Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430FrameLowering.h"
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#include "MSP430InstrInfo.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430Subtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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bool MSP430FrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MF.getFrameInfo()->hasVarSizedObjects() ||
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MFI->isFrameAddressTaken());
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}
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bool MSP430FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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void MSP430FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
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const MSP430InstrInfo &TII =
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*static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Get the number of bytes to allocate from the FrameInfo.
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uint64_t StackSize = MFI->getStackSize();
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uint64_t NumBytes = 0;
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if (hasFP(MF)) {
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// Calculate required stack adjustment
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uint64_t FrameSize = StackSize - 2;
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NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
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// Get the offset of the stack slot for the EBP register... which is
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// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
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// Update the frame offset adjustment.
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MFI->setOffsetAdjustment(-NumBytes);
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// Save FP into the appropriate stack slot...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
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.addReg(MSP430::FP, RegState::Kill);
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// Update FP with the new base value...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
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.addReg(MSP430::SP);
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// Mark the FramePtr as live-in in every block except the entry.
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for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
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I != E; ++I)
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I->addLiveIn(MSP430::FP);
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} else
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NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
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// Skip the callee-saved push instructions.
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while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
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++MBBI;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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if (NumBytes) { // adjust stack pointer: SP -= numbytes
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// If there is an SUB16ri of SP immediately before this instruction, merge
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// the two.
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//NumBytes -= mergeSPUpdates(MBB, MBBI, true);
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// If there is an ADD16ri or SUB16ri of SP immediately after this
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// instruction, merge the two instructions.
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// mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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}
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}
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void MSP430FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
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const MSP430InstrInfo &TII =
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*static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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unsigned RetOpcode = MBBI->getOpcode();
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DebugLoc DL = MBBI->getDebugLoc();
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switch (RetOpcode) {
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case MSP430::RET:
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case MSP430::RETI: break; // These are ok
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default:
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llvm_unreachable("Can only insert epilog into returning blocks");
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}
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// Get the number of bytes to allocate from the FrameInfo
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uint64_t StackSize = MFI->getStackSize();
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unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
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uint64_t NumBytes = 0;
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if (hasFP(MF)) {
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// Calculate required stack adjustment
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uint64_t FrameSize = StackSize - 2;
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NumBytes = FrameSize - CSSize;
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// pop FP.
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
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} else
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NumBytes = StackSize - CSSize;
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// Skip the callee-saved pop instructions.
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while (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PI = std::prev(MBBI);
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unsigned Opc = PI->getOpcode();
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if (Opc != MSP430::POP16r && !PI->isTerminator())
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break;
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--MBBI;
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}
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DL = MBBI->getDebugLoc();
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// If there is an ADD16ri or SUB16ri of SP immediately before this
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// instruction, merge the two instructions.
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//if (NumBytes || MFI->hasVarSizedObjects())
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// mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
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if (MFI->hasVarSizedObjects()) {
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
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if (CSSize) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(CSSize);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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} else {
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// adjust stack pointer back: SP += numbytes
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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}
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}
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// FIXME: Can we eleminate these in favour of generic code?
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bool
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MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>();
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MFI->setCalleeSavedFrameSize(CSI.size() * 2);
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
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.addReg(Reg, RegState::Kill);
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}
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return true;
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}
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bool
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MSP430FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i)
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BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
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return true;
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}
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void MSP430FrameLowering::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const MSP430InstrInfo &TII =
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*static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo());
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unsigned StackAlign = getStackAlignment();
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if (!hasReservedCallFrame(MF)) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub SP, <amt>' and the
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// adjcallstackdown instruction into 'add SP, <amt>'
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// TODO: consider using push / pop instead of sub + store / add
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
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MachineInstr *New = nullptr;
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if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(Amount);
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} else {
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assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
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// factor out the amount the callee already popped.
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uint64_t CalleeAmt = Old->getOperand(1).getImm();
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Amount -= CalleeAmt;
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if (Amount)
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::ADD16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(Amount);
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}
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if (New) {
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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} else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
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// If we are performing frame pointer elimination and if the callee pops
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// something off the stack pointer, add it back.
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if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
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MachineInstr *Old = I;
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MachineInstr *New =
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BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
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MSP430::SP).addReg(MSP430::SP).addImm(CalleeAmt);
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void
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MSP430FrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *) const {
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// Create a frame entry for the FP register that must be saved.
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if (hasFP(MF)) {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
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(void)FrameIdx;
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assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
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"Slot for FP register must be last in order to be found!");
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}
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}
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