mirror of
https://github.com/c64scene-ar/llvm-6502.git
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508c047e71
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243256 91177308-0d34-0410-b5e6-96231b3b80d8
580 lines
29 KiB
TableGen
580 lines
29 KiB
TableGen
//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, referred
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// to here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget state
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//
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def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
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"64-bit mode (x86_64)">;
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def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
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"32-bit mode (80386)">;
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def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
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"16-bit mode (i8086)">;
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features
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//===----------------------------------------------------------------------===//
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions",
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// SSE codegen depends on cmovs, and all
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// SSE1+ processors support them.
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[FeatureMMX, FeatureCMOV]>;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode.
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions",
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[FeatureCMOV]>;
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def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
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"64-bit with cmpxchg16b",
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[Feature64Bit]>;
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def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
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"Bit testing of memory is slow">;
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def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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"SHLD instruction is slow">;
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// FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
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// explicit. Also, it seems this would be the default state for most chips
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// going forward, so it would probably be better to negate the logic and
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// match the 32-byte "slow mem" feature below.
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def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
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"IsUAMemFast", "true",
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"Fast unaligned memory access">;
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def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
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"IsUAMem32Slow", "true",
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"Slow unaligned 32-byte memory access">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions",
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[FeatureSSE3]>;
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def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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"Enable AVX instructions",
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[FeatureSSE42]>;
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
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"Enable AVX-512 instructions",
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[FeatureAVX2]>;
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def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
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"Enable AVX-512 Exponential and Reciprocal Instructions",
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[FeatureAVX512]>;
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def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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"Enable AVX-512 Conflict Detection Instructions",
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[FeatureAVX512]>;
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
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"Enable AVX-512 Doubleword and Quadword Instructions",
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[FeatureAVX512]>;
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def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
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"Enable AVX-512 Byte and Word Instructions",
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[FeatureAVX512]>;
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def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
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"Enable AVX-512 Vector Length eXtensions",
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[FeatureAVX512]>;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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"Enable packed carry-less multiplication instructions",
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[FeatureSSE2]>;
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def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
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"Enable three-operand fused multiple-add",
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[FeatureAVX]>;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add",
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[FeatureAVX, FeatureSSE4A]>;
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def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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"Enable XOP instructions",
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[FeatureFMA4]>;
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def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
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"HasSSEUnalignedMem", "true",
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"Allow unaligned memory operands with SSE instructions">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions",
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[FeatureSSE2]>;
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def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
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"Enable TBM instructions">;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions",
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[FeatureAVX]>;
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def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
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"Support FS/GS Base instructions">;
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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"Support BMI instructions">;
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def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
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"Support BMI2 instructions">;
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def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
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"Support RTM instructions">;
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def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
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"Support HLE">;
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def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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"Support ADX instructions">;
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def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
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"Enable SHA instructions",
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[FeatureSSE2]>;
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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"Support PRFCHW instructions">;
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def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
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"Support RDSEED instruction">;
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def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
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"Support MPX instructions">;
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def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
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"HasSlowDivide32", "true",
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"Use 8-bit divide for positive values less than 256">;
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def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
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"HasSlowDivide64", "true",
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"Use 16-bit divide for positive values less than 65536">;
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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// TODO: This feature ought to be renamed.
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// What it really refers to are CPUs for which certain instructions
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// (which ones besides the example below?) are microcoded.
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// The best examples of this are the memory forms of CALL and PUSH
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// instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
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def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
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"CallRegIndirect", "true",
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"Call register indirect">;
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def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
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"LEA instruction needs inputs at AG stage">;
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def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
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"LEA instruction with certain arguments is slow">;
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def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
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"INC and DEC instructions are slower than ADD and SUB">;
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def FeatureSoftFloat
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: SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software floating point features.">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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include "X86Schedule.td"
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def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
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"Intel Atom processors">;
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def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
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"Intel Silvermont processors">;
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class Proc<string Name, list<SubtargetFeature> Features>
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: ProcessorModel<Name, GenericModel, Features>;
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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def : Proc<"i586", []>;
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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def : Proc<"pentiumpro", [FeatureCMOV]>;
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def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
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def : Proc<"pentium3", [FeatureSSE1]>;
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def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
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def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
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def : Proc<"pentium4", [FeatureSSE2]>;
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def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
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// Intel Core Duo.
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def : ProcessorModel<"yonah", SandyBridgeModel,
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[FeatureSSE3, FeatureSlowBTMem]>;
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// NetBurst.
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def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
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def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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// Intel Core 2 Solo/Duo.
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def : ProcessorModel<"core2", SandyBridgeModel,
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[FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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def : ProcessorModel<"penryn", SandyBridgeModel,
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[FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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// Atom CPUs.
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class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
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ProcIntelAtom,
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FeatureSSSE3,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeatureSlowBTMem,
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FeatureLeaForSP,
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FeatureSlowDivide32,
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FeatureSlowDivide64,
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FeatureCallRegIndirect,
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FeatureLEAUsesAG,
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FeaturePadShortFunctions
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]>;
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def : BonnellProc<"bonnell">;
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def : BonnellProc<"atom">; // Pin the generic name to the baseline.
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class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
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ProcIntelSLM,
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FeatureSSE42,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeaturePOPCNT,
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FeaturePCLMUL,
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FeatureAES,
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FeatureSlowDivide64,
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FeatureCallRegIndirect,
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FeaturePRFCHW,
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FeatureSlowLEA,
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FeatureSlowIncDec,
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FeatureSlowBTMem,
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FeatureFastUAMem
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]>;
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def : SilvermontProc<"silvermont">;
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def : SilvermontProc<"slm">; // Legacy alias.
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// "Arrandale" along with corei3 and corei5
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class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureSSE42,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureFastUAMem,
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FeaturePOPCNT
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]>;
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def : NehalemProc<"nehalem">;
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def : NehalemProc<"corei7">;
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// Westmere is a similar machine to nehalem with some additional features.
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// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
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class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureSSE42,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureFastUAMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL
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]>;
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def : WestmereProc<"westmere">;
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureAVX,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeatureSlowUAMem32,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL
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]>;
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def : SandyBridgeProc<"sandybridge">;
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def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
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class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureAVX,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeatureSlowUAMem32,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase
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]>;
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def : IvyBridgeProc<"ivybridge">;
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def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
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class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureAVX2,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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FeatureSlowIncDec
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]>;
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def : HaswellProc<"haswell">;
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def : HaswellProc<"core-avx2">; // Legacy alias.
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class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureAVX2,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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FeatureADX,
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FeatureRDSEED,
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FeatureSlowIncDec
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]>;
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def : BroadwellProc<"broadwell">;
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// FIXME: define KNL model
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class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
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[FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
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FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
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FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
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FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
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FeatureSlowIncDec, FeatureMPX]>;
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def : KnightsLandingProc<"knl">;
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// FIXME: define SKX model
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class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
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[FeatureAVX512, FeatureCDI,
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FeatureDQI, FeatureBWI, FeatureVLX,
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FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
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FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
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FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
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FeatureSlowIncDec, FeatureMPX]>;
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def : SkylakeProc<"skylake">;
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def : SkylakeProc<"skx">; // Legacy alias.
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// AMD CPUs.
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-3", [Feature3DNow]>;
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def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
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FeatureSlowSHLD]>;
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def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
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FeatureSlowBTMem, FeatureSlowSHLD]>;
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def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"amdfam10", [FeatureSSE4A,
|
|
Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureSlowBTMem,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"barcelona", [FeatureSSE4A,
|
|
Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureSlowBTMem,
|
|
FeatureSlowSHLD]>;
|
|
// Bobcat
|
|
def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
|
|
FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
|
|
FeatureSlowSHLD]>;
|
|
|
|
// Jaguar
|
|
def : ProcessorModel<"btver2", BtVer2Model,
|
|
[FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
|
|
FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
|
|
FeatureBMI, FeatureF16C, FeatureMOVBE,
|
|
FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
|
|
FeatureSlowSHLD]>;
|
|
|
|
// TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
|
|
|
|
// Bulldozer
|
|
def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
|
|
FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
|
|
FeatureAVX, FeatureSSE4A, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureSlowSHLD]>;
|
|
// Piledriver
|
|
def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
|
|
FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
|
|
FeatureAVX, FeatureSSE4A, FeatureF16C,
|
|
FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
|
|
FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
|
|
|
|
// Steamroller
|
|
def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
|
|
FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
|
|
FeatureAVX, FeatureSSE4A, FeatureF16C,
|
|
FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
|
|
FeatureTBM, FeatureFMA, FeatureSlowSHLD,
|
|
FeatureFSGSBase]>;
|
|
|
|
// Excavator
|
|
def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
|
|
FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
|
|
FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureBMI, FeatureBMI2,
|
|
FeatureTBM, FeatureFMA, FeatureSSE4A,
|
|
FeatureFSGSBase]>;
|
|
|
|
def : Proc<"geode", [Feature3DNowA]>;
|
|
|
|
def : Proc<"winchip-c6", [FeatureMMX]>;
|
|
def : Proc<"winchip2", [Feature3DNow]>;
|
|
def : Proc<"c3", [Feature3DNow]>;
|
|
def : Proc<"c3-2", [FeatureSSE1]>;
|
|
|
|
// We also provide a generic 64-bit specific x86 processor model which tries to
|
|
// be good for modern chips without enabling instruction set encodings past the
|
|
// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
|
|
// modern 64-bit x86 chip, and enables features that are generally beneficial.
|
|
//
|
|
// We currently use the Sandy Bridge model as the default scheduling model as
|
|
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
|
|
// covers a huge swath of x86 processors. If there are specific scheduling
|
|
// knobs which need to be tuned differently for AMD chips, we might consider
|
|
// forming a common base for them.
|
|
def : ProcessorModel<"x86-64", SandyBridgeModel,
|
|
[FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
|
|
FeatureFastUAMem]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86RegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86InstrInfo.td"
|
|
|
|
def X86InstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling Conventions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86CallingConv.td"
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly Parser
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ATTAsmParser : AsmParser {
|
|
string AsmParserClassName = "AsmParser";
|
|
}
|
|
|
|
def ATTAsmParserVariant : AsmParserVariant {
|
|
int Variant = 0;
|
|
|
|
// Variant name.
|
|
string Name = "att";
|
|
|
|
// Discard comments in assembly strings.
|
|
string CommentDelimiter = "#";
|
|
|
|
// Recognize hard coded registers.
|
|
string RegisterPrefix = "%";
|
|
}
|
|
|
|
def IntelAsmParserVariant : AsmParserVariant {
|
|
int Variant = 1;
|
|
|
|
// Variant name.
|
|
string Name = "intel";
|
|
|
|
// Discard comments in assembly strings.
|
|
string CommentDelimiter = ";";
|
|
|
|
// Recognize hard coded registers.
|
|
string RegisterPrefix = "";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly Printers
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// The X86 target supports two different syntaxes for emitting machine code.
|
|
// This is controlled by the -x86-asm-syntax={att|intel}
|
|
def ATTAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "ATTInstPrinter";
|
|
int Variant = 0;
|
|
}
|
|
def IntelAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "IntelInstPrinter";
|
|
int Variant = 1;
|
|
}
|
|
|
|
def X86 : Target {
|
|
// Information about the instructions...
|
|
let InstructionSet = X86InstrInfo;
|
|
let AssemblyParsers = [ATTAsmParser];
|
|
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
|
|
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
|
|
}
|