mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-03-12 05:42:47 +00:00
a3313efbbe
------------------------------------------------------------------------ r216064 | kongyi | 2014-08-20 03:40:20 -0700 (Wed, 20 Aug 2014) | 9 lines ARM: Fix codegen for rbit intrinsic LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic. According to ARM ARM, rbit only takes register as argument, not immediate. The correct instruction should be rbit <Rd>, <Rm>. The bug was originally introduced in r211057. Differential Revision: http://reviews.llvm.org/D4980 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@216089 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
394 B
LLVM
21 lines
394 B
LLVM
; RUN: llc -mtriple=armv8-eabi %s -o - | FileCheck %s
|
|
|
|
; CHECK-LABEL: rbit
|
|
; CHECK: rbit r0, r0
|
|
define i32 @rbit(i32 %t) {
|
|
entry:
|
|
%rbit = call i32 @llvm.arm.rbit(i32 %t)
|
|
ret i32 %rbit
|
|
}
|
|
|
|
; CHECK-LABEL: rbit_constant
|
|
; CHECK: mov r0, #0
|
|
; CHECK: rbit r0, r0
|
|
define i32 @rbit_constant() {
|
|
entry:
|
|
%rbit.i = call i32 @llvm.arm.rbit(i32 0)
|
|
ret i32 %rbit.i
|
|
}
|
|
|
|
declare i32 @llvm.arm.rbit(i32)
|