mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-20 11:29:24 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2791 91177308-0d34-0410-b5e6-96231b3b80d8
438 lines
17 KiB
C++
438 lines
17 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// SparcInstrInfo.cpp
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//
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// Purpose:
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//
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// History:
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// 10/15/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "SparcInternals.h"
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#include "SparcInstrSelectionSupport.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/Function.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Instruction.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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using std::vector;
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//************************ Internal Functions ******************************/
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static inline void
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CreateIntSetInstruction(const TargetMachine& target, Function* F,
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int64_t C, Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)
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{
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assert(dest->getType()->isSigned() && "Use CreateUIntSetInstruction()");
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MachineInstr* M;
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uint64_t absC = (C >= 0)? C : -C;
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if (absC > (unsigned int) ~0)
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{ // C does not fit in 32 bits
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TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
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mcfi.addTemp(tmpReg);
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M = new MachineInstr(SETX);
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M->SetMachineOperandConst(0,MachineOperand::MO_SignExtendedImmed,C);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpReg,
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/*isdef*/ true);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
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mvec.push_back(M);
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}
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else
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{
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M = Create2OperandInstr_SImmed(SETSW, C, dest);
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mvec.push_back(M);
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}
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}
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static inline void
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CreateUIntSetInstruction(const TargetMachine& target, Function* F,
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uint64_t C, Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)
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{
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assert(! dest->getType()->isSigned() && "Use CreateIntSetInstruction()");
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unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
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MachineInstr* M;
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if (C > (unsigned int) ~0)
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{ // C does not fit in 32 bits
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assert(dest->getType() == Type::ULongTy && "Sign extension problems");
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TmpInstruction *tmpReg = new TmpInstruction(Type::IntTy);
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mcfi.addTemp(tmpReg);
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M = new MachineInstr(SETX);
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M->SetMachineOperandConst(0, MachineOperand::MO_UnextendedImmed, C);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpReg,
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/*isdef*/ true);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
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mvec.push_back(M);
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}
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else
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{
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// If the destination is smaller than the standard integer reg. size,
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// we have to extend the sign-bit into upper bits of dest, so we
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// need to put the result of the SETUW into a temporary.
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//
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Value* setuwDest = dest;
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if (destSize < target.DataLayout.getIntegerRegize())
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{
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setuwDest = new TmpInstruction(dest, NULL, "setTmp");
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mcfi.addTemp(setuwDest);
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}
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M = Create2OperandInstr_UImmed(SETUW, C, setuwDest);
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mvec.push_back(M);
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if (setuwDest != dest)
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{ // extend the sign-bit of the result into all upper bits of dest
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assert(8*destSize <= 32 &&
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"Unexpected type size > 4 and < IntRegSize?");
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target.getInstrInfo().
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CreateSignExtensionInstructions(target, F,
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setuwDest, 8*destSize, dest,
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mvec, mcfi);
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}
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}
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#define USE_DIRECT_SIGN_EXTENSION_INSTRS
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#ifndef USE_DIRECT_SIGN_EXTENSION_INSTRS
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else
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{ // cast to signed type of the right length and use signed op (SETSW)
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// to get correct sign extension
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//
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minstr = new MachineInstr(SETSW);
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minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
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switch (dest->getType()->getPrimitiveID())
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{
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case Type::UIntTyID:
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minstr->SetMachineOperandConst(0,
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MachineOperand::MO_SignExtendedImmed,
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(int) C);
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break;
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case Type::UShortTyID:
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minstr->SetMachineOperandConst(0,
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MachineOperand::MO_SignExtendedImmed,
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(short) C);
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break;
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case Type::UByteTyID:
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minstr->SetMachineOperandConst(0,
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MachineOperand::MO_SignExtendedImmed,
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(char) C);
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break;
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default:
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assert(0 && "Unexpected unsigned type");
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break;
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}
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}
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#endif USE_DIRECT_SIGN_EXTENSION_INSTRS
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}
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//************************* External Classes *******************************/
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class MachineInstrInfo.
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//---------------------------------------------------------------------------
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/*ctor*/
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UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
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: MachineInstrInfo(tgt, SparcMachineInstrDesc,
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/*descSize = */ NUM_TOTAL_OPCODES,
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/*numRealOpCodes = */ NUM_REAL_OPCODES)
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{
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}
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//
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via MachineCodeForMethod.
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//
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void
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UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const
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{
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assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
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"I only know about constant values and global addresses");
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// Use a "set" instruction for known constants that can go in an integer reg.
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// Use a "load" instruction for all other constants, in particular,
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// floating point constants and addresses of globals.
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//
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const Type* valType = val->getType();
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if (valType->isIntegral() || valType == Type::BoolTy)
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{
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if (! val->getType()->isSigned())
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{
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uint64_t C = cast<ConstantUInt>(val)->getValue();
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CreateUIntSetInstruction(target, F, C, dest, mvec, mcfi);
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}
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else
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{
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bool isValidConstant;
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int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
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assert(isValidConstant && "Unrecognized constant");
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CreateIntSetInstruction(target, F, C, dest, mvec, mcfi);
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}
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}
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else
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{
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// Make an instruction sequence to load the constant, viz:
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// SETX <addr-of-constant>, tmpReg, addrReg
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// LOAD /*addr*/ addrReg, /*offset*/ 0, dest
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// Only the SETX is needed if `val' is a GlobalValue, i.e,. it is
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// itself a constant address. Otherwise, both are needed.
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Value* addrVal;
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int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
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TmpInstruction* tmpReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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mcfi.addTemp(tmpReg);
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if (isa<Constant>(val))
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{
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// Create another TmpInstruction for the hidden integer register
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TmpInstruction* addrReg =
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new TmpInstruction(PointerType::get(val->getType()), val);
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mcfi.addTemp(addrReg);
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addrVal = addrReg;
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}
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else
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addrVal = dest;
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MachineInstr* M = new MachineInstr(SETX);
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M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, val);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpReg,
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/*isdef*/ true);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, addrVal);
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mvec.push_back(M);
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if (isa<Constant>(val))
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{
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// Make sure constant is emitted to constant pool in assembly code.
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MachineCodeForMethod::get(F).addToConstantPool(cast<Constant>(val));
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// Generate the load instruction
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M = Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
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addrVal, zeroOffset, dest);
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mvec.push_back(M);
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}
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}
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}
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via MachineCodeForMethod.
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//
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void
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UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const
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{
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assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
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&& "Source type must be integral");
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assert(dest->getType()->isFloatingPoint()
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&& "Dest type must be float/double");
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int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
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// Store instruction stores `val' to [%fp+offset].
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// The store and load opCodes are based on the value being copied, and
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// they use integer and float types that accomodate the
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// larger of the source type and the destination type:
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// On SparcV9: int for float, long for double.
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//
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Type* tmpType = (dest->getType() == Type::FloatTy)? Type::IntTy
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: Type::LongTy;
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MachineInstr* store = new MachineInstr(ChooseStoreInstruction(tmpType));
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store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
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store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
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store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
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mvec.push_back(store);
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// Load instruction loads [%fp+offset] to `dest'.
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//
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MachineInstr* load =new MachineInstr(ChooseLoadInstruction(dest->getType()));
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load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
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load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
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load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
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mvec.push_back(load);
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}
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via MachineCodeForMethod.
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//
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void
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UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const
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{
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assert(val->getType()->isFloatingPoint()
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&& "Source type must be float/double");
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assert((dest->getType()->isIntegral() || isa<PointerType>(dest->getType()))
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&& "Dest type must be integral");
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int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
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// Store instruction stores `val' to [%fp+offset].
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// The store and load opCodes are based on the value being copied, and
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// they use the integer type that matches the source type in size:
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// On SparcV9: int for float, long for double.
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//
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Type* tmpType = (val->getType() == Type::FloatTy)? Type::IntTy
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: Type::LongTy;
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MachineInstr* store=new MachineInstr(ChooseStoreInstruction(val->getType()));
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store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
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store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
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store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
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mvec.push_back(store);
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// Load instruction loads [%fp+offset] to `dest'.
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//
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MachineInstr* load = new MachineInstr(ChooseLoadInstruction(tmpType));
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load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
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load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
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load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
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mvec.push_back(load);
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}
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via MachineCodeForMethod.
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//
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void
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UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
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Function *F,
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Value* src,
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Instruction* dest,
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vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const
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{
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bool loadConstantToReg = false;
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const Type* resultType = dest->getType();
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MachineOpCode opCode = ChooseAddInstructionByType(resultType);
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if (opCode == INVALID_OPCODE)
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{
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assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
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return;
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}
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// if `src' is a constant that doesn't fit in the immed field or if it is
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// a global variable (i.e., a constant address), generate a load
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// instruction instead of an add
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//
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if (isa<Constant>(src))
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{
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unsigned int machineRegNum;
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int64_t immedValue;
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MachineOperand::MachineOperandType opType =
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ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
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machineRegNum, immedValue);
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if (opType == MachineOperand::MO_VirtualRegister)
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loadConstantToReg = true;
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}
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else if (isa<GlobalValue>(src))
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loadConstantToReg = true;
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if (loadConstantToReg)
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{ // `src' is constant and cannot fit in immed field for the ADD
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// Insert instructions to "load" the constant into a register
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target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
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mvec, mcfi);
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}
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else
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{ // Create an add-with-0 instruction of the appropriate type.
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// Make `src' the second operand, in case it is a constant
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// Use (unsigned long) 0 for a NULL pointer value.
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//
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const Type* zeroValueType =
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isa<PointerType>(resultType) ? Type::ULongTy : resultType;
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MachineInstr* minstr =
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Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
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src, dest);
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mvec.push_back(minstr);
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}
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}
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// For SPARC v9, we sign-extend the given unsigned operand using SLL; SRA.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via MachineCodeForMethod.
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//
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void
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UltraSparcInstrInfo::CreateSignExtensionInstructions(
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const TargetMachine& target,
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Function* F,
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Value* unsignedSrcVal,
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unsigned int srcSizeInBits,
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Value* dest,
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vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const
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{
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MachineInstr* M;
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assert(srcSizeInBits > 0 && srcSizeInBits <= 32
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&& "Hmmm... srcSizeInBits > 32 unexpected but could be handled here.");
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if (srcSizeInBits < 32)
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{ // SLL is needed since operand size is < 32 bits.
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TmpInstruction *tmpI = new TmpInstruction(dest->getType(),
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unsignedSrcVal, dest,"make32");
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mcfi.addTemp(tmpI);
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M = Create3OperandInstr_UImmed(SLL,unsignedSrcVal,32-srcSizeInBits,tmpI);
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mvec.push_back(M);
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unsignedSrcVal = tmpI;
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}
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M = Create3OperandInstr_UImmed(SRA, unsignedSrcVal, 32-srcSizeInBits, dest);
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mvec.push_back(M);
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}
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