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28f02fdd76
the base pointer, without the offset. This matches MemSDNode's new alignment behavior, and holds more interesting information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82473 91177308-0d34-0410-b5e6-96231b3b80d8
241 lines
9.0 KiB
C++
241 lines
9.0 KiB
C++
//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfoImpl class, it just provides default
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// implementations of various methods.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// commuteInstruction - The default implementation of this method just exchanges
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// the two operands returned by findCommutedOpIndices.
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MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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bool HasDef = TID.getNumDefs();
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if (HasDef && !MI->getOperand(0).isReg())
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// No idea how to commute this instruction. Target should implement its own.
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return 0;
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unsigned Idx1, Idx2;
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if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Don't know how to commute: " << *MI;
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llvm_report_error(Msg.str());
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}
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assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(Idx1).getReg();
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unsigned Reg2 = MI->getOperand(Idx2).getReg();
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bool Reg1IsKill = MI->getOperand(Idx1).isKill();
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bool Reg2IsKill = MI->getOperand(Idx2).isKill();
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bool ChangeReg0 = false;
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if (HasDef && MI->getOperand(0).getReg() == Reg1) {
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// Must be two address instruction!
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assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
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"Expecting a two-address instruction!");
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Reg2IsKill = false;
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ChangeReg0 = true;
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}
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = HasDef
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? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
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bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
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MachineFunction &MF = *MI->getParent()->getParent();
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if (HasDef)
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return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
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.addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
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.addReg(Reg2, getKillRegState(Reg2IsKill))
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.addReg(Reg1, getKillRegState(Reg2IsKill));
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else
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return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
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.addReg(Reg2, getKillRegState(Reg2IsKill))
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.addReg(Reg1, getKillRegState(Reg2IsKill));
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}
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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MI->getOperand(Idx2).setReg(Reg1);
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MI->getOperand(Idx1).setReg(Reg2);
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MI->getOperand(Idx2).setIsKill(Reg1IsKill);
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MI->getOperand(Idx1).setIsKill(Reg2IsKill);
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return MI;
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}
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/// findCommutedOpIndices - If specified MI is commutable, return the two
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/// operand indices that would swap value. Return true if the instruction
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/// is not in a form which this routine understands.
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bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
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unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isCommutable())
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return false;
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// This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
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// is not true, then the target must implement this.
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SrcOpIdx1 = TID.getNumDefs();
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SrcOpIdx2 = SrcOpIdx1 + 1;
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if (!MI->getOperand(SrcOpIdx1).isReg() ||
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!MI->getOperand(SrcOpIdx2).isReg())
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// No idea.
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return false;
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return true;
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}
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bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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bool MadeChange = false;
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isPredicable())
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return false;
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (TID.OpInfo[i].isPredicate()) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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MO.setReg(Pred[j].getReg());
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MadeChange = true;
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} else if (MO.isImm()) {
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MO.setImm(Pred[j].getImm());
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MadeChange = true;
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} else if (MO.isMBB()) {
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MO.setMBB(Pred[j].getMBB());
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MadeChange = true;
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}
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++j;
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}
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}
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return MadeChange;
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}
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void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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unsigned SubIdx,
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const MachineInstr *Orig) const {
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MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
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MachineOperand &MO = MI->getOperand(0);
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MO.setReg(DestReg);
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MO.setSubReg(SubIdx);
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MBB.insert(I, MI);
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}
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bool TargetInstrInfoImpl::isDeadInstruction(const MachineInstr *MI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
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TID.isCall() || TID.isBarrier() || TID.isReturn() ||
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TID.hasUnmodeledSideEffects())
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return false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.getReg())
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continue;
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if (MO.isDef() && !MO.isDead())
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return false;
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if (MO.isUse() && MO.isKill())
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// FIXME: We can't remove kill markers or else the scavenger will assert.
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// An alternative is to add a ADD pseudo instruction to replace kill
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// markers.
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return false;
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}
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return true;
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}
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unsigned
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TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
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unsigned FnSize = 0;
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for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
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MBBI != E; ++MBBI) {
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const MachineBasicBlock &MBB = *MBBI;
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for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
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I != E; ++I)
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FnSize += GetInstSizeInBytes(I);
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}
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return FnSize;
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}
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/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
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/// slot into the specified machine instruction for the specified operand(s).
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/// If this is possible, a new instruction is returned with the specified
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/// operand folded, otherwise NULL is returned. The client is responsible for
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/// removing the old instruction and adding the new one in the instruction
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/// stream.
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MachineInstr*
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TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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unsigned Flags = 0;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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if (MI->getOperand(Ops[i]).isDef())
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Flags |= MachineMemOperand::MOStore;
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else
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Flags |= MachineMemOperand::MOLoad;
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// Ask the target to do the actual folding.
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MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
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if (!NewMI) return 0;
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assert((!(Flags & MachineMemOperand::MOStore) ||
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NewMI->getDesc().mayStore()) &&
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"Folded a def to a non-store!");
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assert((!(Flags & MachineMemOperand::MOLoad) ||
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NewMI->getDesc().mayLoad()) &&
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"Folded a use to a non-load!");
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const MachineFrameInfo &MFI = *MF.getFrameInfo();
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assert(MFI.getObjectOffset(FrameIndex) != -1);
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MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FrameIndex),
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Flags,
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/*Offset=*/0,
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MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlignment(FrameIndex));
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NewMI->addMemOperand(MF, MMO);
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return NewMI;
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}
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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MachineInstr*
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TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
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#ifndef NDEBUG
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
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#endif
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// Ask the target to do the actual folding.
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MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
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if (!NewMI) return 0;
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// Copy the memoperands from the load to the folded instruction.
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for (std::list<MachineMemOperand>::iterator I = LoadMI->memoperands_begin(),
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E = LoadMI->memoperands_end(); I != E; ++I)
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NewMI->addMemOperand(MF, *I);
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return NewMI;
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}
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