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cd52a7a381
Apparently, the style needs to be agreed upon first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240390 91177308-0d34-0410-b5e6-96231b3b80d8
544 lines
21 KiB
C++
544 lines
21 KiB
C++
//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64RegisterInfo.h"
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#include "MCTargetDesc/AArch64FixupKinds.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MachO.h"
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using namespace llvm;
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namespace {
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class AArch64AsmBackend : public MCAsmBackend {
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static const unsigned PCRelFlagVal =
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
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public:
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AArch64AsmBackend(const Target &T) : MCAsmBackend() {}
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unsigned getNumFixupKinds() const override {
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return AArch64::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// AArch64FixupKinds.h.
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//
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// Name Offset (bits) Size (bits) Flags
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{ "fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal },
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{ "fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal },
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{ "fixup_aarch64_add_imm12", 10, 12, 0 },
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{ "fixup_aarch64_ldst_imm12_scale1", 10, 12, 0 },
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{ "fixup_aarch64_ldst_imm12_scale2", 10, 12, 0 },
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{ "fixup_aarch64_ldst_imm12_scale4", 10, 12, 0 },
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{ "fixup_aarch64_ldst_imm12_scale8", 10, 12, 0 },
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{ "fixup_aarch64_ldst_imm12_scale16", 10, 12, 0 },
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{ "fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal },
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{ "fixup_aarch64_movw", 5, 16, 0 },
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{ "fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal },
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{ "fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal },
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{ "fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal },
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{ "fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal },
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{ "fixup_aarch64_tlsdesc_call", 0, 0, 0 }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value, bool IsPCRel) const override;
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bool mayNeedRelaxation(const MCInst &Inst) const override;
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override;
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
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void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
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unsigned getPointerSize() const { return 8; }
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};
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} // end anonymous namespace
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/// \brief The number of bytes the fixup may change.
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case AArch64::fixup_aarch64_tlsdesc_call:
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return 0;
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case FK_Data_1:
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return 1;
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case FK_Data_2:
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case AArch64::fixup_aarch64_movw:
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return 2;
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case AArch64::fixup_aarch64_pcrel_branch14:
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case AArch64::fixup_aarch64_add_imm12:
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case AArch64::fixup_aarch64_ldst_imm12_scale1:
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case AArch64::fixup_aarch64_ldst_imm12_scale2:
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case AArch64::fixup_aarch64_ldst_imm12_scale4:
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case AArch64::fixup_aarch64_ldst_imm12_scale8:
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case AArch64::fixup_aarch64_ldst_imm12_scale16:
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case AArch64::fixup_aarch64_ldr_pcrel_imm19:
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case AArch64::fixup_aarch64_pcrel_branch19:
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return 3;
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case AArch64::fixup_aarch64_pcrel_adr_imm21:
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case AArch64::fixup_aarch64_pcrel_adrp_imm21:
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case AArch64::fixup_aarch64_pcrel_branch26:
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case AArch64::fixup_aarch64_pcrel_call26:
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case FK_Data_4:
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return 4;
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case FK_Data_8:
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return 8;
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}
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}
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static unsigned AdrImmBits(unsigned Value) {
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unsigned lo2 = Value & 0x3;
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unsigned hi19 = (Value & 0x1ffffc) >> 2;
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return (hi19 << 5) | (lo2 << 29);
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}
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static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
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int64_t SignedValue = static_cast<int64_t>(Value);
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case AArch64::fixup_aarch64_pcrel_adr_imm21:
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if (SignedValue > 2097151 || SignedValue < -2097152)
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report_fatal_error("fixup value out of range");
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return AdrImmBits(Value & 0x1fffffULL);
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case AArch64::fixup_aarch64_pcrel_adrp_imm21:
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return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
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case AArch64::fixup_aarch64_ldr_pcrel_imm19:
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case AArch64::fixup_aarch64_pcrel_branch19:
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// Signed 21-bit immediate
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if (SignedValue > 2097151 || SignedValue < -2097152)
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report_fatal_error("fixup value out of range");
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// Low two bits are not encoded.
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return (Value >> 2) & 0x7ffff;
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case AArch64::fixup_aarch64_add_imm12:
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case AArch64::fixup_aarch64_ldst_imm12_scale1:
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// Unsigned 12-bit immediate
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if (Value >= 0x1000)
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report_fatal_error("invalid imm12 fixup value");
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return Value;
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case AArch64::fixup_aarch64_ldst_imm12_scale2:
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// Unsigned 12-bit immediate which gets multiplied by 2
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if (Value & 1 || Value >= 0x2000)
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report_fatal_error("invalid imm12 fixup value");
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return Value >> 1;
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case AArch64::fixup_aarch64_ldst_imm12_scale4:
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// Unsigned 12-bit immediate which gets multiplied by 4
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if (Value & 3 || Value >= 0x4000)
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report_fatal_error("invalid imm12 fixup value");
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return Value >> 2;
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case AArch64::fixup_aarch64_ldst_imm12_scale8:
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// Unsigned 12-bit immediate which gets multiplied by 8
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if (Value & 7 || Value >= 0x8000)
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report_fatal_error("invalid imm12 fixup value");
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return Value >> 3;
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case AArch64::fixup_aarch64_ldst_imm12_scale16:
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// Unsigned 12-bit immediate which gets multiplied by 16
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if (Value & 15 || Value >= 0x10000)
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report_fatal_error("invalid imm12 fixup value");
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return Value >> 4;
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case AArch64::fixup_aarch64_movw:
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report_fatal_error("no resolvable MOVZ/MOVK fixups supported yet");
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return Value;
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case AArch64::fixup_aarch64_pcrel_branch14:
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// Signed 16-bit immediate
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if (SignedValue > 32767 || SignedValue < -32768)
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report_fatal_error("fixup value out of range");
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// Low two bits are not encoded (4-byte alignment assumed).
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if (Value & 0x3)
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report_fatal_error("fixup not sufficiently aligned");
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return (Value >> 2) & 0x3fff;
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case AArch64::fixup_aarch64_pcrel_branch26:
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case AArch64::fixup_aarch64_pcrel_call26:
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// Signed 28-bit immediate
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if (SignedValue > 134217727 || SignedValue < -134217728)
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report_fatal_error("fixup value out of range");
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// Low two bits are not encoded (4-byte alignment assumed).
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if (Value & 0x3)
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report_fatal_error("fixup not sufficiently aligned");
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return (Value >> 2) & 0x3ffffff;
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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return Value;
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}
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}
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void AArch64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value,
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bool IsPCRel) const {
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unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
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if (!Value)
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return; // Doesn't change encoding.
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MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
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// Apply any target-specific value adjustments.
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Value = adjustFixupValue(Fixup.getKind(), Value);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned Offset = Fixup.getOffset();
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assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned i = 0; i != NumBytes; ++i)
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Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
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}
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bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
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return false;
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}
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bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const {
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// FIXME: This isn't correct for AArch64. Just moving the "generic" logic
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// into the targets for now.
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//
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// Relax if the value is too big for a (signed) i8.
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return int64_t(Value) != int64_t(int8_t(Value));
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}
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void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
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MCInst &Res) const {
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llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
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}
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bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// If the count is not 4-byte aligned, we must be writing data into the text
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// section (otherwise we have unaligned instructions, and thus have far
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// bigger problems), so just write zeros instead.
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OW->WriteZeros(Count % 4);
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// We are properly aligned, so write NOPs as requested.
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Count /= 4;
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for (uint64_t i = 0; i != Count; ++i)
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OW->write32(0xd503201f);
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return true;
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}
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namespace {
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namespace CU {
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/// \brief Compact unwind encoding values.
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enum CompactUnwindEncodings {
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/// \brief A "frameless" leaf function, where no non-volatile registers are
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/// saved. The return remains in LR throughout the function.
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UNWIND_AArch64_MODE_FRAMELESS = 0x02000000,
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/// \brief No compact unwind encoding available. Instead the low 23-bits of
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/// the compact unwind encoding is the offset of the DWARF FDE in the
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/// __eh_frame section. This mode is never used in object files. It is only
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/// generated by the linker in final linked images, which have only DWARF info
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/// for a function.
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UNWIND_AArch64_MODE_DWARF = 0x03000000,
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/// \brief This is a standard arm64 prologue where FP/LR are immediately
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/// pushed on the stack, then SP is copied to FP. If there are any
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/// non-volatile register saved, they are copied into the stack fame in pairs
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/// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
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/// five X pairs and four D pairs can be saved, but the memory layout must be
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/// in register number order.
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UNWIND_AArch64_MODE_FRAME = 0x04000000,
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/// \brief Frame register pair encodings.
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UNWIND_AArch64_FRAME_X19_X20_PAIR = 0x00000001,
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UNWIND_AArch64_FRAME_X21_X22_PAIR = 0x00000002,
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UNWIND_AArch64_FRAME_X23_X24_PAIR = 0x00000004,
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UNWIND_AArch64_FRAME_X25_X26_PAIR = 0x00000008,
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UNWIND_AArch64_FRAME_X27_X28_PAIR = 0x00000010,
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UNWIND_AArch64_FRAME_D8_D9_PAIR = 0x00000100,
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UNWIND_AArch64_FRAME_D10_D11_PAIR = 0x00000200,
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UNWIND_AArch64_FRAME_D12_D13_PAIR = 0x00000400,
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UNWIND_AArch64_FRAME_D14_D15_PAIR = 0x00000800
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};
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} // end CU namespace
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// FIXME: This should be in a separate file.
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class DarwinAArch64AsmBackend : public AArch64AsmBackend {
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const MCRegisterInfo &MRI;
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/// \brief Encode compact unwind stack adjustment for frameless functions.
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/// See UNWIND_AArch64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
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/// The stack size always needs to be 16 byte aligned.
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uint32_t encodeStackAdjustment(uint32_t StackSize) const {
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return (StackSize / 16) << 12;
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}
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public:
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DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
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: AArch64AsmBackend(T), MRI(MRI) {}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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return createAArch64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64,
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MachO::CPU_SUBTYPE_ARM64_ALL);
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}
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/// \brief Generate the compact unwind encoding from the CFI directives.
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uint32_t generateCompactUnwindEncoding(
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ArrayRef<MCCFIInstruction> Instrs) const override {
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if (Instrs.empty())
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return CU::UNWIND_AArch64_MODE_FRAMELESS;
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bool HasFP = false;
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unsigned StackSize = 0;
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uint32_t CompactUnwindEncoding = 0;
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for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
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const MCCFIInstruction &Inst = Instrs[i];
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switch (Inst.getOperation()) {
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default:
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// Cannot handle this directive: bail out.
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return CU::UNWIND_AArch64_MODE_DWARF;
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case MCCFIInstruction::OpDefCfa: {
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// Defines a frame pointer.
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assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) ==
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AArch64::FP &&
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"Invalid frame pointer!");
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assert(i + 2 < e && "Insufficient CFI instructions to define a frame!");
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const MCCFIInstruction &LRPush = Instrs[++i];
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assert(LRPush.getOperation() == MCCFIInstruction::OpOffset &&
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"Link register not pushed!");
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const MCCFIInstruction &FPPush = Instrs[++i];
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assert(FPPush.getOperation() == MCCFIInstruction::OpOffset &&
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"Frame pointer not pushed!");
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unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
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unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
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LRReg = getXRegFromWReg(LRReg);
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FPReg = getXRegFromWReg(FPReg);
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assert(LRReg == AArch64::LR && FPReg == AArch64::FP &&
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"Pushing invalid registers for frame!");
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// Indicate that the function has a frame.
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CompactUnwindEncoding |= CU::UNWIND_AArch64_MODE_FRAME;
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HasFP = true;
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break;
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}
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case MCCFIInstruction::OpDefCfaOffset: {
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assert(StackSize == 0 && "We already have the CFA offset!");
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StackSize = std::abs(Inst.getOffset());
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break;
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}
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case MCCFIInstruction::OpOffset: {
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// Registers are saved in pairs. We expect there to be two consecutive
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// `.cfi_offset' instructions with the appropriate registers specified.
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unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
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if (i + 1 == e)
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return CU::UNWIND_AArch64_MODE_DWARF;
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const MCCFIInstruction &Inst2 = Instrs[++i];
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if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
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return CU::UNWIND_AArch64_MODE_DWARF;
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unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
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// N.B. The encodings must be in register number order, and the X
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// registers before the D registers.
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// X19/X20 pair = 0x00000001,
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// X21/X22 pair = 0x00000002,
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// X23/X24 pair = 0x00000004,
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// X25/X26 pair = 0x00000008,
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// X27/X28 pair = 0x00000010
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Reg1 = getXRegFromWReg(Reg1);
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Reg2 = getXRegFromWReg(Reg2);
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if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
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(CompactUnwindEncoding & 0xF1E) == 0)
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CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_X19_X20_PAIR;
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else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
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(CompactUnwindEncoding & 0xF1C) == 0)
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CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_X21_X22_PAIR;
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else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
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(CompactUnwindEncoding & 0xF18) == 0)
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CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_X23_X24_PAIR;
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else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
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(CompactUnwindEncoding & 0xF10) == 0)
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CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_X25_X26_PAIR;
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else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
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(CompactUnwindEncoding & 0xF00) == 0)
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CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_X27_X28_PAIR;
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else {
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Reg1 = getDRegFromBReg(Reg1);
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Reg2 = getDRegFromBReg(Reg2);
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// D8/D9 pair = 0x00000100,
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// D10/D11 pair = 0x00000200,
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// D12/D13 pair = 0x00000400,
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// D14/D15 pair = 0x00000800
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if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
|
|
(CompactUnwindEncoding & 0xE00) == 0)
|
|
CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_D8_D9_PAIR;
|
|
else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
|
|
(CompactUnwindEncoding & 0xC00) == 0)
|
|
CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_D10_D11_PAIR;
|
|
else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&
|
|
(CompactUnwindEncoding & 0x800) == 0)
|
|
CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_D12_D13_PAIR;
|
|
else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
|
|
CompactUnwindEncoding |= CU::UNWIND_AArch64_FRAME_D14_D15_PAIR;
|
|
else
|
|
// A pair was pushed which we cannot handle.
|
|
return CU::UNWIND_AArch64_MODE_DWARF;
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!HasFP) {
|
|
// With compact unwind info we can only represent stack adjustments of up
|
|
// to 65520 bytes.
|
|
if (StackSize > 65520)
|
|
return CU::UNWIND_AArch64_MODE_DWARF;
|
|
|
|
CompactUnwindEncoding |= CU::UNWIND_AArch64_MODE_FRAMELESS;
|
|
CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
|
|
}
|
|
|
|
return CompactUnwindEncoding;
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
namespace {
|
|
|
|
class ELFAArch64AsmBackend : public AArch64AsmBackend {
|
|
public:
|
|
uint8_t OSABI;
|
|
bool IsLittleEndian;
|
|
|
|
ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian)
|
|
: AArch64AsmBackend(T), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {}
|
|
|
|
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
|
|
return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian);
|
|
}
|
|
|
|
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
|
|
const MCFixup &Fixup, const MCFragment *DF,
|
|
const MCValue &Target, uint64_t &Value,
|
|
bool &IsResolved) override;
|
|
|
|
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
|
|
uint64_t Value, bool IsPCRel) const override;
|
|
};
|
|
|
|
void ELFAArch64AsmBackend::processFixupValue(
|
|
const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup,
|
|
const MCFragment *DF, const MCValue &Target, uint64_t &Value,
|
|
bool &IsResolved) {
|
|
// The ADRP instruction adds some multiple of 0x1000 to the current PC &
|
|
// ~0xfff. This means that the required offset to reach a symbol can vary by
|
|
// up to one step depending on where the ADRP is in memory. For example:
|
|
//
|
|
// ADRP x0, there
|
|
// there:
|
|
//
|
|
// If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
|
|
// we'll need that as an offset. At any other address "there" will be in the
|
|
// same page as the ADRP and the instruction should encode 0x0. Assuming the
|
|
// section isn't 0x1000-aligned, we therefore need to delegate this decision
|
|
// to the linker -- a relocation!
|
|
if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
|
|
IsResolved = false;
|
|
}
|
|
|
|
// Returns whether this fixup is based on an address in the .eh_frame section,
|
|
// and therefore should be byte swapped.
|
|
// FIXME: Should be replaced with something more principled.
|
|
static bool isByteSwappedFixup(const MCExpr *E) {
|
|
MCValue Val;
|
|
if (!E->evaluateAsRelocatable(Val, nullptr, nullptr))
|
|
return false;
|
|
|
|
if (!Val.getSymA() || Val.getSymA()->getSymbol().isUndefined())
|
|
return false;
|
|
|
|
const MCSectionELF *SecELF =
|
|
dyn_cast<MCSectionELF>(&Val.getSymA()->getSymbol().getSection());
|
|
return SecELF->getSectionName() == ".eh_frame";
|
|
}
|
|
|
|
void ELFAArch64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
|
|
unsigned DataSize, uint64_t Value,
|
|
bool IsPCRel) const {
|
|
// store fixups in .eh_frame section in big endian order
|
|
if (!IsLittleEndian && Fixup.getKind() == FK_Data_4) {
|
|
if (isByteSwappedFixup(Fixup.getValue()))
|
|
Value = ByteSwap_32(unsigned(Value));
|
|
}
|
|
AArch64AsmBackend::applyFixup (Fixup, Data, DataSize, Value, IsPCRel);
|
|
}
|
|
}
|
|
|
|
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
|
|
const MCRegisterInfo &MRI,
|
|
const Triple &TheTriple,
|
|
StringRef CPU) {
|
|
if (TheTriple.isOSBinFormatMachO())
|
|
return new DarwinAArch64AsmBackend(T, MRI);
|
|
|
|
assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
|
return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true);
|
|
}
|
|
|
|
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
|
|
const MCRegisterInfo &MRI,
|
|
const Triple &TheTriple,
|
|
StringRef CPU) {
|
|
assert(TheTriple.isOSBinFormatELF() &&
|
|
"Big endian is only supported for ELF targets!");
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
|
return new ELFAArch64AsmBackend(T, OSABI,
|
|
/*IsLittleEndian=*/false);
|
|
}
|