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1ff585db47
Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8
//===-- README.txt - Notes for WebAssembly code gen -----------------------===// This WebAssembly backend is presently in a very early stage of development. The code should build and not break anything else, but don't expect a lot more at this point. For more information on WebAssembly itself, see the design documents: * https://github.com/WebAssembly/design/blob/master/README.md The following documents contain some information on the planned semantics and binary encoding of WebAssembly itself: * https://github.com/WebAssembly/design/blob/master/AstSemantics.md * https://github.com/WebAssembly/design/blob/master/BinaryEncoding.md //===---------------------------------------------------------------------===//