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5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
659 B
LLVM
21 lines
659 B
LLVM
; RUN: llc -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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define float @test_sqrt_f32(float %a) {
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; CHECK-LABEL: test_sqrt_f32
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; CHECK: fsqrt s0, s0
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%res = call float @llvm.sqrt.f32(float %a)
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ret float %res
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}
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declare float @llvm.sqrt.f32(float) nounwind readnone
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define double @test_sqrt_f64(double %a) {
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; CHECK-LABEL: test_sqrt_f64
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; CHECK: fsqrt d0, d0
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%res = call double @llvm.sqrt.f64(double %a)
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ret double %res
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}
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declare double @llvm.sqrt.f64(double) nounwind readnone
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