mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b503b49b51
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
2.4 KiB
LLVM
103 lines
2.4 KiB
LLVM
; Test additions between an i64 and a zero-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check ALGFR.
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define i64 @f1(i64 %a, i32 %b) {
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; CHECK: f1:
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; CHECK: algfr %r2, %r3
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check ALGF with no displacement.
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define i64 @f2(i64 %a, i32 *%src) {
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; CHECK: f2:
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; CHECK: algf %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i32 *%src
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the high end of the aligned ALGF range.
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define i64 @f3(i64 %a, i32 *%src) {
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; CHECK: f3:
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; CHECK: algf %r2, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%b = load i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f4(i64 %a, i32 *%src) {
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; CHECK: f4:
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; CHECK: agfi %r3, 524288
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; CHECK: algf %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%b = load i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the high end of the negative aligned ALGF range.
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define i64 @f5(i64 %a, i32 *%src) {
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; CHECK: f5:
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; CHECK: algf %r2, -4(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%b = load i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the low end of the ALGF range.
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define i64 @f6(i64 %a, i32 *%src) {
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; CHECK: f6:
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; CHECK: algf %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%b = load i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i64 %a, i32 *%src) {
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; CHECK: f7:
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; CHECK: agfi %r3, -524292
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; CHECK: algf %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%b = load i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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; Check that ALGF allows an index.
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define i64 @f8(i64 %a, i64 %src, i64 %index) {
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; CHECK: f8:
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; CHECK: algf %r2, 524284({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%bext = zext i32 %b to i64
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%add = add i64 %a, %bext
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ret i64 %add
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}
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