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00e08fcaa0
Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215558 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.1 KiB
C++
69 lines
2.1 KiB
C++
//===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
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#include "AMDGPUMachineFunction.h"
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#include <map>
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namespace llvm {
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class MachineRegisterInfo;
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/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
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/// tells the hardware which interpolation parameters to load.
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class SIMachineFunctionInfo : public AMDGPUMachineFunction {
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void anchor() override;
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public:
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struct SpilledReg {
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unsigned VGPR;
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int Lane;
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SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
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SpilledReg() : VGPR(0), Lane(-1) { }
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bool hasLane() { return Lane != -1;}
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};
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struct RegSpillTracker {
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private:
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unsigned CurrentLane;
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std::map<unsigned, SpilledReg> SpilledRegisters;
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public:
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unsigned LaneVGPR;
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RegSpillTracker() : CurrentLane(0), SpilledRegisters(), LaneVGPR(0) { }
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/// \p NumRegs The number of consecutive registers what need to be spilled.
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/// This function will ensure that all registers are stored in
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/// the same VGPR.
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/// \returns The lane to be used for storing the first register.
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unsigned reserveLanes(MachineRegisterInfo &MRI, MachineFunction *MF,
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unsigned NumRegs = 1);
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void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
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const SpilledReg& getSpilledReg(unsigned FrameIndex);
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bool programSpillsRegisters() { return !SpilledRegisters.empty(); }
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};
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// SIMachineFunctionInfo definition
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SIMachineFunctionInfo(const MachineFunction &MF);
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unsigned PSInputAddr;
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struct RegSpillTracker SpillTracker;
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unsigned NumUserSGPRs;
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};
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} // End namespace llvm
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#endif
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