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https://github.com/c64scene-ar/llvm-6502.git
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6035518e3b
shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
331 lines
10 KiB
C++
331 lines
10 KiB
C++
//===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the XCore implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreRegisterInfo.h"
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#include "XCore.h"
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#include "XCoreInstrInfo.h"
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#include "XCoreMachineFunctionInfo.h"
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#include "XCoreSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "xcore-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "XCoreGenRegisterInfo.inc"
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XCoreRegisterInfo::XCoreRegisterInfo()
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: XCoreGenRegisterInfo(XCore::LR) {
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}
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// helper functions
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static inline bool isImmUs(unsigned val) {
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return val <= 11;
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}
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static inline bool isImmU6(unsigned val) {
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return val < (1 << 6);
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}
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static inline bool isImmU16(unsigned val) {
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return val < (1 << 16);
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}
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static void InsertFPImmInst(MachineBasicBlock::iterator II,
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const XCoreInstrInfo &TII,
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unsigned Reg, unsigned FrameReg, int Offset ) {
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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switch (MI.getOpcode()) {
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
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.addReg(FrameReg)
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addReg(FrameReg)
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
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.addReg(FrameReg)
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.addImm(Offset);
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break;
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default:
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llvm_unreachable("Unexpected Opcode");
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}
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}
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static void InsertFPConstInst(MachineBasicBlock::iterator II,
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const XCoreInstrInfo &TII,
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unsigned Reg, unsigned FrameReg,
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int Offset, RegScavenger *RS ) {
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assert(RS && "requiresRegisterScavenging failed");
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
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RS->setRegUsed(ScratchOffset);
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TII.loadImmediate(MBB, II, ScratchOffset, Offset);
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switch (MI.getOpcode()) {
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
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.addReg(FrameReg)
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addReg(FrameReg)
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
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.addReg(FrameReg)
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.addReg(ScratchOffset, RegState::Kill);
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break;
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default:
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llvm_unreachable("Unexpected Opcode");
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}
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}
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static void InsertSPImmInst(MachineBasicBlock::iterator II,
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const XCoreInstrInfo &TII,
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unsigned Reg, int Offset) {
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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bool isU6 = isImmU6(Offset);
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switch (MI.getOpcode()) {
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int NewOpcode;
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case XCore::LDWFI:
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NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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.addImm(Offset);
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break;
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default:
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llvm_unreachable("Unexpected Opcode");
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}
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}
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static void InsertSPConstInst(MachineBasicBlock::iterator II,
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const XCoreInstrInfo &TII,
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unsigned Reg, int Offset, RegScavenger *RS ) {
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assert(RS && "requiresRegisterScavenging failed");
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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unsigned OpCode = MI.getOpcode();
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unsigned ScratchBase;
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if (OpCode==XCore::STWFI) {
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ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
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RS->setRegUsed(ScratchBase);
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} else
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ScratchBase = Reg;
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
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unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
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RS->setRegUsed(ScratchOffset);
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TII.loadImmediate(MBB, II, ScratchOffset, Offset);
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switch (OpCode) {
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
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.addReg(ScratchBase, RegState::Kill)
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addReg(ScratchBase, RegState::Kill)
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
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.addReg(ScratchBase, RegState::Kill)
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.addReg(ScratchOffset, RegState::Kill);
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break;
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default:
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llvm_unreachable("Unexpected Opcode");
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}
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}
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bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
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return MF.getMMI().hasDebugInfo() ||
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MF.getFunction()->needsUnwindTableEntry();
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}
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const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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// The callee saved registers LR & FP are explicitly handled during
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// emitPrologue & emitEpilogue and related functions.
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static const MCPhysReg CalleeSavedRegs[] = {
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XCore::R4, XCore::R5, XCore::R6, XCore::R7,
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XCore::R8, XCore::R9, XCore::R10,
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0
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};
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static const MCPhysReg CalleeSavedRegsFP[] = {
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XCore::R4, XCore::R5, XCore::R6, XCore::R7,
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XCore::R8, XCore::R9,
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0
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};
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const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
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if (TFI->hasFP(*MF))
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return CalleeSavedRegsFP;
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return CalleeSavedRegs;
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}
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BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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Reserved.set(XCore::CP);
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Reserved.set(XCore::DP);
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Reserved.set(XCore::SP);
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Reserved.set(XCore::LR);
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if (TFI->hasFP(MF)) {
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Reserved.set(XCore::R10);
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}
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return Reserved;
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}
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bool
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XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool
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XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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return true;
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}
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bool
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XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
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return false;
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}
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void
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XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
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int FrameIndex = FrameOp.getIndex();
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MachineFunction &MF = *MI.getParent()->getParent();
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const XCoreInstrInfo &TII =
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*static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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int StackSize = MF.getFrameInfo()->getStackSize();
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#ifndef NDEBUG
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DEBUG(errs() << "\nFunction : "
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<< MF.getName() << "\n");
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DEBUG(errs() << "<--------->\n");
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DEBUG(MI.print(errs()));
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
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DEBUG(errs() << "FrameOffset : " << Offset << "\n");
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DEBUG(errs() << "StackSize : " << StackSize << "\n");
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#endif
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Offset += StackSize;
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unsigned FrameReg = getFrameRegister(MF);
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// Special handling of DBG_VALUE instructions.
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if (MI.isDebugValue()) {
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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return;
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}
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// fold constant into offset.
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
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assert(Offset%4 == 0 && "Misaligned stack offset");
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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Offset/=4;
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unsigned Reg = MI.getOperand(0).getReg();
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assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
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if (TFI->hasFP(MF)) {
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if (isImmUs(Offset))
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InsertFPImmInst(II, TII, Reg, FrameReg, Offset);
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else
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InsertFPConstInst(II, TII, Reg, FrameReg, Offset, RS);
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} else {
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if (isImmU16(Offset))
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InsertSPImmInst(II, TII, Reg, Offset);
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else
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InsertSPConstInst(II, TII, Reg, Offset, RS);
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}
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// Erase old instruction.
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MachineBasicBlock &MBB = *MI.getParent();
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MBB.erase(II);
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}
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unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
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}
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