mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-04 07:29:20 +00:00
14a926f13b
The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182920 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
2.2 KiB
LLVM
104 lines
2.2 KiB
LLVM
; Test 32-bit comparisons in which the second operand is zero-extended
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; from a PC-relative i16.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i16 1
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@h = global i16 1, align 1, section "foo"
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; Check unsigned comparison.
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define i32 @f1(i32 %src1) {
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; CHECK: f1:
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; CHECK: clhrl %r2, g
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Check signed comparison.
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define i32 @f2(i32 %src1) {
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; CHECK: f2:
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; CHECK-NOT: clhrl
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; CHECK: br %r14
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entry:
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%val = load i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp slt i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Check equality.
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define i32 @f3(i32 %src1) {
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; CHECK: f3:
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; CHECK: clhrl %r2, g
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; CHECK-NEXT: je
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; CHECK: br %r14
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entry:
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%val = load i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp eq i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Check inequality.
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define i32 @f4(i32 %src1) {
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; CHECK: f4:
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; CHECK: clhrl %r2, g
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; CHECK-NEXT: jlh
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; CHECK: br %r14
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entry:
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%val = load i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp ne i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Repeat f1 with an unaligned address.
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define i32 @f5(i32 %src1) {
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; CHECK: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
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; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: clr %r2, [[VAL]]
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i16 *@h, align 1
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%src2 = zext i16 %val to i32
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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