mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 06:29:45 +00:00
to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
163 lines
5.3 KiB
C++
163 lines
5.3 KiB
C++
//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "msp430-reg-info"
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#include "MSP430RegisterInfo.h"
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#include "MSP430.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#define GET_REGINFO_TARGET_DESC
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#include "MSP430GenRegisterInfo.inc"
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using namespace llvm;
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// FIXME: Provide proper call frame setup / destroy opcodes.
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MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
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const TargetInstrInfo &tii)
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: MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
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StackAlign = TM.getFrameLowering()->getStackAlignment();
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}
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const uint16_t*
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MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
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const Function* F = MF->getFunction();
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static const uint16_t CalleeSavedRegs[] = {
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MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
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MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
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0
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};
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static const uint16_t CalleeSavedRegsFP[] = {
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MSP430::R5W, MSP430::R6W, MSP430::R7W,
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MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
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0
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};
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static const uint16_t CalleeSavedRegsIntr[] = {
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MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
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MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
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MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
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0
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};
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static const uint16_t CalleeSavedRegsIntrFP[] = {
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MSP430::R5W, MSP430::R6W, MSP430::R7W,
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MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
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MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
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0
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};
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if (TFI->hasFP(*MF))
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return (F->getCallingConv() == CallingConv::MSP430_INTR ?
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CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
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else
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return (F->getCallingConv() == CallingConv::MSP430_INTR ?
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CalleeSavedRegsIntr : CalleeSavedRegs);
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}
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BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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// Mark 4 special registers with subregisters as reserved.
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Reserved.set(MSP430::PCB);
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Reserved.set(MSP430::SPB);
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Reserved.set(MSP430::SRB);
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Reserved.set(MSP430::CGB);
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Reserved.set(MSP430::PCW);
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Reserved.set(MSP430::SPW);
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Reserved.set(MSP430::SRW);
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Reserved.set(MSP430::CGW);
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// Mark frame pointer as reserved if needed.
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if (TFI->hasFP(MF))
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Reserved.set(MSP430::FPW);
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return Reserved;
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}
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const TargetRegisterClass *
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MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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return &MSP430::GR16RegClass;
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}
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void
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MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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DebugLoc dl = MI.getDebugLoc();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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// Skip the saved PC
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Offset += 2;
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if (!TFI->hasFP(MF))
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Offset += MF.getFrameInfo()->getStackSize();
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else
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Offset += 2; // Skip the saved FPW
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// Fold imm into offset
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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if (MI.getOpcode() == MSP430::ADD16ri) {
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// This is actually "load effective address" of the stack slot
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// instruction. We have only two-address instructions, thus we need to
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// expand it into mov + add
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MI.setDesc(TII.get(MSP430::MOV16rr));
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MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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if (Offset == 0)
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return;
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// We need to materialize the offset via add instruction.
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unsigned DstReg = MI.getOperand(0).getReg();
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if (Offset < 0)
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BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
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.addReg(DstReg).addImm(-Offset);
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else
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BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
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.addReg(DstReg).addImm(Offset);
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return;
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}
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MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
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}
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