llvm-6502/test/CodeGen/NVPTX
Justin Holewinski 5443e7d790 [NVPTX] Re-enable support for virtual registers in the final output
Now that 3.3 is branched, we are re-enabling virtual registers to help
iron out bugs before the next release. Some of the post-RA passes do
not play well with virtual registers, so we disable them for now. The
needed functionality of the PrologEpilogInserter pass is copied to a
new backend-specific NVPTXPrologEpilog pass.

The test for this commit is not breaking the existing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 12:14:49 +00:00
..
annotations.ll
arithmetic-fp-sm20.ll
arithmetic-int.ll
calling-conv.ll
compare-int.ll
convert-fp.ll
convert-int-sm20.ll
fma-disable.ll
fma.ll
generic-to-nvvm.ll
global-ordering.ll
i1-global.ll
i1-param.ll
intrin-nocapture.ll
intrinsic-old.ll [NVPTX] Re-enable support for virtual registers in the final output 2013-05-31 12:14:49 +00:00
intrinsics.ll [NVPTX] Re-enable support for virtual registers in the final output 2013-05-31 12:14:49 +00:00
ld-addrspace.ll
ld-generic.ll
lit.local.cfg
load-sext-i1.ll
nvvm-reflect.ll
param-align.ll
pr13291-i1-store.ll
ptx-version-30.ll
ptx-version-31.ll
refl1.ll
sched1.ll
sched2.ll
simple-call.ll
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-35.ll
st-addrspace.ll
st-generic.ll
tuple-literal.ll
vector-args.ll
vector-compare.ll
vector-loads.ll
vector-select.ll