llvm-6502/lib/CodeGen/SelectionDAG
Chris Lattner 01426e1a27 Fix gcc.c-torture/compile/920520-1.c by inserting bitconverts
for strange asm conditions earlier.  In this case, we have a
double being passed in an integer reg class.  Convert to like
sized integer register so that we allocate the right number 
for the class (two i32's for the f64 in this case).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57862 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-21 00:45:36 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp
FastISel.cpp
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
SelectionDAG.cpp
SelectionDAGBuild.cpp Fix gcc.c-torture/compile/920520-1.c by inserting bitconverts 2008-10-21 00:45:36 +00:00
SelectionDAGBuild.h
SelectionDAGISel.cpp
SelectionDAGPrinter.cpp
TargetLowering.cpp