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https://github.com/c64scene-ar/llvm-6502.git
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Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0. This makes sharing code for pre/postRA passes more robust. Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA(). To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs(). PEI resets virtual regs when it's done scavenging. PTX will either have to provide its own PEI pass or assign physregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151032 91177308-0d34-0410-b5e6-96231b3b80d8
168 lines
5.9 KiB
C++
168 lines
5.9 KiB
C++
//===-- PTXTargetMachine.cpp - Define TargetMachine for PTX ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace llvm {
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MCStreamer *createPTXAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
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bool isVerboseAsm, bool useLoc,
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bool useCFI, bool useDwarfDirectory,
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MCInstPrinter *InstPrint,
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MCCodeEmitter *CE,
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MCAsmBackend *MAB,
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bool ShowInst);
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}
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extern "C" void LLVMInitializePTXTarget() {
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RegisterTargetMachine<PTX32TargetMachine> X(ThePTX32Target);
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RegisterTargetMachine<PTX64TargetMachine> Y(ThePTX64Target);
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TargetRegistry::RegisterAsmStreamer(ThePTX32Target, createPTXAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(ThePTX64Target, createPTXAsmStreamer);
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}
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namespace {
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const char* DataLayout32 =
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"e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
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const char* DataLayout64 =
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"e-p:64:64-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
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}
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// DataLayout and FrameLowering are filled with dummy data
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PTXTargetMachine::PTXTargetMachine(const Target &T,
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StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64Bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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DataLayout(is64Bit ? DataLayout64 : DataLayout32),
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Subtarget(TT, CPU, FS, is64Bit),
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FrameLowering(Subtarget),
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InstrInfo(*this),
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TSInfo(*this),
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TLInfo(*this) {
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}
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void PTX32TargetMachine::anchor() { }
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PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void PTX64TargetMachine::anchor() { }
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PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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namespace llvm {
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/// PTX Code Generator Pass Configuration Options.
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class PTXPassConfig : public TargetPassConfig {
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public:
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PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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PTXTargetMachine &getPTXTargetMachine() const {
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return getTM<PTXTargetMachine>();
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}
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bool addInstSelector();
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FunctionPass *createTargetRegisterAllocator(bool);
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void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
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bool addPostRegAlloc();
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void addMachineLateOptimization();
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bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) {
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PTXPassConfig *PassConfig = new PTXPassConfig(this, PM);
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PassConfig->disablePass(PrologEpilogCodeInserterID);
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return PassConfig;
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}
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bool PTXPassConfig::addInstSelector() {
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PM.add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
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return false;
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}
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FunctionPass *PTXPassConfig::createTargetRegisterAllocator(bool /*Optimized*/) {
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return createPTXRegisterAllocator();
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}
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// Modify the optimized compilation path to bypass optimized register alloction.
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void PTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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addFastRegAlloc(RegAllocPass);
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}
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bool PTXPassConfig::addPostRegAlloc() {
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// PTXMFInfoExtract must after register allocation!
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//PM.add(createPTXMFInfoExtract(getPTXTargetMachine()));
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return false;
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}
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/// Add passes that optimize machine instructions after register allocation.
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void PTXPassConfig::addMachineLateOptimization() {
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if (addPass(BranchFolderPassID) != &NoPassID)
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printNoVerify("After BranchFolding");
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if (addPass(TailDuplicateID) != &NoPassID)
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printNoVerify("After TailDuplicate");
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}
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bool PTXPassConfig::addPreEmitPass() {
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PM.add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
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PM.add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
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return true;
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}
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