mirror of
https://github.com/c64scene-ar/llvm-6502.git
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01657f390d
Summary: One of the calls to AllocateStack (the one in LowerCall) doesn't look like it should be there but it was there before and removing it breaks the frame size calculation. Reviewers: vmedic, theraven Reviewed By: theraven Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221529 91177308-0d34-0410-b5e6-96231b3b80d8
554 lines
20 KiB
C++
554 lines
20 KiB
C++
//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
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#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Target/TargetLowering.h"
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#include <deque>
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#include <string>
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namespace llvm {
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namespace MipsISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Jump and link (call)
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JmpLink,
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// Tail call
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TailCall,
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// Get the Higher 16 bits from a 32-bit immediate
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// No relation with Mips Hi register
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Hi,
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// Get the Lower 16 bits from a 32-bit immediate
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// No relation with Mips Lo register
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Lo,
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// Thread Pointer
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ThreadPointer,
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// Floating Point Branch Conditional
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FPBrcond,
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// Floating Point Compare
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FPCmp,
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// Floating Point Conditional Moves
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CMovFP_T,
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CMovFP_F,
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// FP-to-int truncation node.
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TruncIntFP,
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// Return
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Ret,
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EH_RETURN,
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// Node used to extract integer from accumulator.
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MFHI,
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MFLO,
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// Node used to insert integers to accumulator.
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MTLOHI,
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// Mult nodes.
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Mult,
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Multu,
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// MAdd/Sub nodes
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MAdd,
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MAddu,
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MSub,
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MSubu,
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// DivRem(u)
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DivRem,
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DivRemU,
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DivRem16,
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DivRemU16,
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BuildPairF64,
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ExtractElementF64,
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Wrapper,
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DynAlloc,
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Sync,
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Ext,
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Ins,
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// EXTR.W instrinsic nodes.
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EXTP,
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EXTPDP,
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EXTR_S_H,
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EXTR_W,
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EXTR_R_W,
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EXTR_RS_W,
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SHILO,
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MTHLIP,
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// DPA.W intrinsic nodes.
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MULSAQ_S_W_PH,
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MAQ_S_W_PHL,
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MAQ_S_W_PHR,
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MAQ_SA_W_PHL,
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MAQ_SA_W_PHR,
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DPAU_H_QBL,
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DPAU_H_QBR,
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DPSU_H_QBL,
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DPSU_H_QBR,
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DPAQ_S_W_PH,
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DPSQ_S_W_PH,
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DPAQ_SA_L_W,
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DPSQ_SA_L_W,
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DPA_W_PH,
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DPS_W_PH,
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DPAQX_S_W_PH,
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DPAQX_SA_W_PH,
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DPAX_W_PH,
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DPSX_W_PH,
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DPSQX_S_W_PH,
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DPSQX_SA_W_PH,
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MULSA_W_PH,
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MULT,
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MULTU,
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MADD_DSP,
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MADDU_DSP,
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MSUB_DSP,
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MSUBU_DSP,
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// DSP shift nodes.
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SHLL_DSP,
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SHRA_DSP,
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SHRL_DSP,
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// DSP setcc and select_cc nodes.
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SETCC_DSP,
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SELECT_CC_DSP,
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// Vector comparisons.
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// These take a vector and return a boolean.
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VALL_ZERO,
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VANY_ZERO,
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VALL_NONZERO,
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VANY_NONZERO,
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// These take a vector and return a vector bitmask.
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VCEQ,
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VCLE_S,
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VCLE_U,
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VCLT_S,
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VCLT_U,
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// Element-wise vector max/min.
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VSMAX,
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VSMIN,
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VUMAX,
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VUMIN,
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// Vector Shuffle with mask as an operand
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VSHF, // Generic shuffle
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SHF, // 4-element set shuffle.
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ILVEV, // Interleave even elements
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ILVOD, // Interleave odd elements
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ILVL, // Interleave left elements
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ILVR, // Interleave right elements
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PCKEV, // Pack even elements
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PCKOD, // Pack odd elements
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// Vector Lane Copy
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INSVE, // Copy element from one vector to another
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// Combined (XOR (OR $a, $b), -1)
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VNOR,
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// Extended vector element extraction
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VEXTRACT_SEXT_ELT,
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VEXTRACT_ZEXT_ELT,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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SWL,
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SWR,
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LDL,
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LDR,
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SDL,
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SDR
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MipsFunctionInfo;
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class MipsSubtarget;
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class MipsCCState;
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class MipsTargetLowering : public TargetLowering {
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bool isMicroMips;
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public:
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explicit MipsTargetLowering(const MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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static const MipsTargetLowering *create(const MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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/// createFastISel - This method returns a target specific FastISel object,
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/// or null if the target does not support "fast" ISel.
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) const override;
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MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
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void LowerOperationWrapper(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const override;
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const override;
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struct LTStr {
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bool operator()(const char *S1, const char *S2) const {
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return strcmp(S1, S2) < 0;
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}
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};
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void HandleByVal(CCState *, unsigned &, unsigned) const override;
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protected:
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SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
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// This method creates the following nodes, which are necessary for
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// computing a local symbol's address:
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//
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// (add (load (wrapper $gp, %got(sym)), %lo(sym))
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template <class NodeTy>
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SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
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bool IsN32OrN64) const {
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SDLoc DL(N);
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unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
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SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
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getTargetNode(N, Ty, DAG, GOTFlag));
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SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
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MachinePointerInfo::getGOT(), false, false,
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false, 0);
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unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
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SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
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getTargetNode(N, Ty, DAG, LoFlag));
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return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
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}
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// This method creates the following nodes, which are necessary for
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// computing a global symbol's address:
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//
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// (load (wrapper $gp, %got(sym)))
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template<class NodeTy>
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SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
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unsigned Flag, SDValue Chain,
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const MachinePointerInfo &PtrInfo) const {
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SDLoc DL(N);
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SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
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getTargetNode(N, Ty, DAG, Flag));
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return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
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}
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// This method creates the following nodes, which are necessary for
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// computing a global symbol's address in large-GOT mode:
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//
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// (load (wrapper (add %hi(sym), $gp), %lo(sym)))
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template<class NodeTy>
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SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
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unsigned HiFlag, unsigned LoFlag,
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SDValue Chain,
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const MachinePointerInfo &PtrInfo) const {
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SDLoc DL(N);
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SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
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getTargetNode(N, Ty, DAG, HiFlag));
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Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
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SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
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getTargetNode(N, Ty, DAG, LoFlag));
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return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
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0);
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}
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// This method creates the following nodes, which are necessary for
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// computing a symbol's address in non-PIC mode:
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//
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// (add %hi(sym), %lo(sym))
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template<class NodeTy>
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SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
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SDLoc DL(N);
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SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
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SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
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return DAG.getNode(ISD::ADD, DL, Ty,
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DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
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DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
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}
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// This method creates the following nodes, which are necessary for
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// computing a symbol's address using gp-relative addressing:
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//
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// (add $gp, %gp_rel(sym))
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template<class NodeTy>
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SDValue getAddrGPRel(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
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SDLoc DL(N);
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assert(Ty == MVT::i32);
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SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
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return DAG.getNode(ISD::ADD, DL, Ty,
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DAG.getRegister(Mips::GP, Ty),
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DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
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GPRel));
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}
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/// This function fills Ops, which is the list of operands that will later
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/// be used when a function call node is created. It also generates
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/// copyToReg nodes to set up argument registers.
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virtual void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
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SDValue Chain) const;
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protected:
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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// Subtarget Info
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const MipsSubtarget &Subtarget;
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private:
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// Create a TargetGlobalAddress node.
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SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
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unsigned Flag) const;
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// Create a TargetExternalSymbol node.
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SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
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unsigned Flag) const;
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// Create a TargetBlockAddress node.
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SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
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unsigned Flag) const;
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// Create a TargetJumpTable node.
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SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
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unsigned Flag) const;
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// Create a TargetConstantPool node.
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SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
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unsigned Flag) const;
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// Lower Operand helpers
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
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TargetLowering::CallLoweringInfo &CLI) const;
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// Lower Operand specifics
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SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
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SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
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bool IsSRA) const;
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SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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/// isEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization.
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virtual bool
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isEligibleForTailCallOptimization(const CCState &CCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo &FI) const = 0;
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/// copyByValArg - Copy argument registers which were used to pass a byval
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/// argument to the stack. Create a stack frame object for the byval
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/// argument.
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void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
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SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
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SmallVectorImpl<SDValue> &InVals,
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const Argument *FuncArg, unsigned FirstReg,
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unsigned LastReg, const CCValAssign &VA,
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MipsCCState &State) const;
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/// passByValArg - Pass a byval argument in registers or on stack.
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void passByValArg(SDValue Chain, SDLoc DL,
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std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
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SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
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MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
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unsigned FirstReg, unsigned LastReg,
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const ISD::ArgFlagsTy &Flags, bool isLittle,
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const CCValAssign &VA) const;
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/// writeVarArgRegs - Write variable function arguments passed in registers
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/// to the stack. Also create a stack frame object for the first variable
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/// argument.
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void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
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SDLoc DL, SelectionDAG &DAG, CCState &State) const;
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SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
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SDValue Arg, SDLoc DL, bool IsTailCall,
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SelectionDAG &DAG) const;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc dl, SelectionDAG &DAG) const override;
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// Inline asm support
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const override;
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/// This function parses registers that appear in inline-asm constraints.
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/// It returns pair (0, 0) on failure.
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std::pair<unsigned, const TargetRegisterClass *>
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parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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|
MVT VT) const override;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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|
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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void LowerAsmOperandForConstraint(SDValue Op,
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|
std::string &Constraint,
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|
std::vector<SDValue> &Ops,
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|
SelectionDAG &DAG) const override;
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bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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|
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
|
|
unsigned SrcAlign,
|
|
bool IsMemset, bool ZeroMemset,
|
|
bool MemcpyStrSrc,
|
|
MachineFunction &MF) const override;
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|
|
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/// isFPImmLegal - Returns true if the target can instruction select the
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|
/// specified FP immediate natively. If false, the legalizer will
|
|
/// materialize the FP immediate as a load from a constant pool.
|
|
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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|
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unsigned getJumpTableEncoding() const override;
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/// Emit a sign-extension using sll/sra, seb, or seh appropriately.
|
|
MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
|
|
MachineBasicBlock *BB,
|
|
unsigned Size, unsigned DstReg,
|
|
unsigned SrcRec) const;
|
|
|
|
MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
|
|
unsigned Size, unsigned BinOpcode, bool Nand = false) const;
|
|
MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
|
|
MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
|
|
bool Nand = false) const;
|
|
MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
|
|
MachineBasicBlock *BB, unsigned Size) const;
|
|
MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
|
|
MachineBasicBlock *BB, unsigned Size) const;
|
|
MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
|
|
};
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|
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/// Create MipsTargetLowering objects.
|
|
const MipsTargetLowering *
|
|
createMips16TargetLowering(const MipsTargetMachine &TM,
|
|
const MipsSubtarget &STI);
|
|
const MipsTargetLowering *
|
|
createMipsSETargetLowering(const MipsTargetMachine &TM,
|
|
const MipsSubtarget &STI);
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|
|
|
namespace Mips {
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo);
|
|
}
|
|
}
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#endif
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