mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70726 91177308-0d34-0410-b5e6-96231b3b80d8
570 lines
25 KiB
TableGen
570 lines
25 KiB
TableGen
//===- MSP430InstrInfo.td - MSP430 Instruction defs -----------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the MSP430 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "MSP430InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Type Constraints.
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//===----------------------------------------------------------------------===//
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class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
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class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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//===----------------------------------------------------------------------===//
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// Type Profiles.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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//===----------------------------------------------------------------------===//
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def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
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//===----------------------------------------------------------------------===//
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// MSP430 Operand Definitions.
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//===----------------------------------------------------------------------===//
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// Address operands
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def memsrc : Operand<i16> {
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let PrintMethod = "printSrcMemOperand";
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let MIOperandInfo = (ops i16imm, GR16);
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}
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def memdst : Operand<i16> {
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let PrintMethod = "printSrcMemOperand";
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let MIOperandInfo = (ops i16imm, GR16);
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}
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//===----------------------------------------------------------------------===//
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// MSP430 Complex Pattern Definitions.
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//===----------------------------------------------------------------------===//
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def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
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//===----------------------------------------------------------------------===//
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// Pattern Fragments
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def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
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def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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let neverHasSideEffects = 1 in
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def NOP : Pseudo<(outs), (ins), "nop", []>;
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//===----------------------------------------------------------------------===//
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// Real Instructions
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1 in {
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def RETI : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
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}
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//===----------------------------------------------------------------------===//
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// Move Instructions
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// FIXME: Provide proper encoding!
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let neverHasSideEffects = 1 in {
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def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[]>;
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def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[]>;
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}
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// FIXME: Provide proper encoding!
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(set GR8:$dst, imm:$src)]>;
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def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, imm:$src)]>;
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}
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(set GR8:$dst, (load addr:$src))]>;
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def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (load addr:$src))]>;
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}
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def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (zext GR8:$src))]>;
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def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
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def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(store (i8 imm:$src), addr:$dst)]>;
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def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[(store (i16 imm:$src), addr:$dst)]>;
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def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(store GR8:$src, addr:$dst)]>;
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def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[(store GR16:$src, addr:$dst)]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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let isTwoAddress = 1 in {
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let Defs = [SRW] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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// FIXME: Provide proper encoding!
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def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (add GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def ADD8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def ADD16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def ADD8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADD16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADD8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"add.b\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def ADD16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"add.w\t{$src, $dst|$dst, $src}",
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[(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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let Uses = [SRW] in {
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let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
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def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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} // isCommutable
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def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def ADC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def ADC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def ADC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def ADC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"addc.b\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def ADC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"addc.w\t{$src, $dst|$dst, $src}",
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[(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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} // Uses = [SRW]
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (and GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def AND8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def AND16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def AND8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def AND16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def AND8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"and.b\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"and.w\t{$src, $dst|$dst, $src}",
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[(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
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def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isTwoAddress = 0 in {
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def XOR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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def XOR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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def XOR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def XOR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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def XOR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"xor.b\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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def XOR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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"xor.w\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
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(implicit SRW)]>;
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}
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def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"sub.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
|
|
(implicit SRW)]>;
|
|
|
|
def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|
"sub.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
|
|
(implicit SRW)]>;
|
|
def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
|
"sub.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
|
|
(implicit SRW)]>;
|
|
|
|
def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
|
|
"sub.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
|
|
(implicit SRW)]>;
|
|
def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
|
|
"sub.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
|
|
(implicit SRW)]>;
|
|
|
|
let isTwoAddress = 0 in {
|
|
def SUB8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
|
|
"sub.b\t{$src, $dst|$dst, $src}",
|
|
[(store (sub (load addr:$dst), GR8:$src), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def SUB16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
|
|
"sub.w\t{$src, $dst|$dst, $src}",
|
|
[(store (sub (load addr:$dst), GR16:$src), addr:$dst),
|
|
(implicit SRW)]>;
|
|
|
|
def SUB8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
|
|
"sub.b\t{$src, $dst|$dst, $src}",
|
|
[(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def SUB16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
|
|
"sub.w\t{$src, $dst|$dst, $src}",
|
|
[(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
|
(implicit SRW)]>;
|
|
|
|
def SUB8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
|
"sub.b\t{$src, $dst|$dst, $src}",
|
|
[(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def SUB16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
|
"sub.w\t{$src, $dst|$dst, $src}",
|
|
[(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
|
(implicit SRW)]>;
|
|
}
|
|
|
|
let Uses = [SRW] in {
|
|
def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|
"subc.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
|
|
(implicit SRW)]>;
|
|
def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|
"subc.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
|
|
(implicit SRW)]>;
|
|
|
|
def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|
"subc.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
|
|
(implicit SRW)]>;
|
|
def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
|
"subc.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
|
|
(implicit SRW)]>;
|
|
|
|
def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
|
|
"subc.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
|
|
(implicit SRW)]>;
|
|
def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
|
|
"subc.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
|
|
(implicit SRW)]>;
|
|
|
|
let isTwoAddress = 0 in {
|
|
def SBC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
|
|
"subc.b\t{$src, $dst|$dst, $src}",
|
|
[(store (sube (load addr:$dst), GR8:$src), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def SBC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
|
|
"subc.w\t{$src, $dst|$dst, $src}",
|
|
[(store (sube (load addr:$dst), GR16:$src), addr:$dst),
|
|
(implicit SRW)]>;
|
|
|
|
def SBC8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
|
|
"subc.b\t{$src, $dst|$dst, $src}",
|
|
[(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def SBC16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
|
|
"subc.w\t{$src, $dst|$dst, $src}",
|
|
[(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
|
(implicit SRW)]>;
|
|
|
|
def SBC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
|
"subc.b\t{$src, $dst|$dst, $src}",
|
|
[(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def SBC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
|
"subc.w\t{$src, $dst|$dst, $src}",
|
|
[(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
|
(implicit SRW)]>;
|
|
}
|
|
|
|
} // Uses = [SRW]
|
|
|
|
// FIXME: Provide proper encoding!
|
|
def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
|
|
"rra.w\t$dst",
|
|
[(set GR16:$dst, (MSP430rra GR16:$src)),
|
|
(implicit SRW)]>;
|
|
|
|
def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
|
|
"sxt\t$dst",
|
|
[(set GR16:$dst, (sext_inreg GR16:$src, i8)),
|
|
(implicit SRW)]>;
|
|
|
|
//def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
|
|
// "sxt\t$dst",
|
|
// [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
|
|
// (implicit SRW)]>;
|
|
|
|
} // Defs = [SRW]
|
|
|
|
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
|
|
def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|
"bis.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
|
|
def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|
"bis.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
|
|
}
|
|
|
|
def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|
"bis.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
|
|
def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
|
"bis.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
|
|
|
|
def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
|
|
"bis.b\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
|
|
def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
|
|
"bis.w\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
|
|
|
|
let isTwoAddress = 0 in {
|
|
def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
|
|
"bis.b\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), GR8:$src), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
|
|
"bis.w\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), GR16:$src), addr:$dst),
|
|
(implicit SRW)]>;
|
|
|
|
def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
|
|
"bis.b\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
|
|
"bis.w\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
|
(implicit SRW)]>;
|
|
|
|
def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
|
"bis.b\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
|
(implicit SRW)]>;
|
|
def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
|
|
"bis.w\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
|
(implicit SRW)]>;
|
|
}
|
|
|
|
} // isTwoAddress = 1
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
|
|
// extload
|
|
def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
|
|
|
|
// truncs
|
|
def : Pat<(i8 (trunc GR16:$src)),
|
|
(EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
|