llvm-6502/lib/CodeGen
Evan Cheng 197d19d11c Notes on re-materialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35420 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 08:30:04 +00:00
..
SelectionDAG Scale 1 is always ok. 2007-03-28 01:55:52 +00:00
AsmPrinter.cpp Small eye-candy: use asciz directive everywhere, where possible. 2007-03-06 19:25:02 +00:00
BranchFolding.cpp maintain LiveIn when splitting blocks (register scavenging needs it) 2007-03-20 21:35:06 +00:00
DwarfWriter.cpp Cleanup: make SetCounter an instance variable 2007-03-07 08:25:02 +00:00
ELFWriter.cpp Generalize TargetData strings, to support more interesting forms of data. 2007-02-14 05:52:17 +00:00
ELFWriter.h Moved from include/llvm/CodeGen to lib/CodeGen. 2007-02-08 01:30:50 +00:00
IntrinsicLowering.cpp Lower eh filter intrinsic. 2007-03-01 20:24:30 +00:00
LiveInterval.cpp Added an automatic cast to "std::ostream*" etc. from OStream. We then can 2006-12-17 05:15:13 +00:00
LiveIntervalAnalysis.cpp Move rematerialization out of beta. 2007-03-28 08:26:40 +00:00
LiveVariables.cpp Track the BB's where each virtual register is used. 2007-03-17 09:29:54 +00:00
LLVMTargetMachine.cpp Now LoopStrengthReduce is a LoopPass. 2007-03-06 21:14:09 +00:00
MachineBasicBlock.cpp Print preds / succs BB numbers. 2007-03-09 08:29:08 +00:00
MachineFunction.cpp Generalize TargetData strings, to support more interesting forms of data. 2007-02-14 05:52:17 +00:00
MachineInstr.cpp Change findRegisterUseOperand() to return operand index instead. 2007-03-26 22:37:45 +00:00
MachineModuleInfo.cpp Collect eh filter info. 2007-03-01 20:25:32 +00:00
MachinePassRegistry.cpp Final polish on machine pass registries. 2006-08-02 12:30:23 +00:00
MachOWriter.cpp Remove unneeded header file. 2007-03-04 04:41:04 +00:00
MachOWriter.h More Mach-O writer improvements. 2007-02-28 07:40:50 +00:00
Makefile this will work better 2006-11-03 19:15:55 +00:00
Passes.cpp *** empty log message *** 2006-11-16 20:11:33 +00:00
PHIElimination.cpp Keep UsedBlocks info accurate. 2007-03-18 09:02:31 +00:00
PhysRegTracker.h
PrologEpilogInserter.cpp If target decides to create an emergency spill slot, make sure it's closest to SP or frame pointer. 2007-03-06 10:02:38 +00:00
README.txt Notes on re-materialization. 2007-03-28 08:30:04 +00:00
RegAllocLinearScan.cpp First cut trivial re-materialization support. 2007-03-20 08:13:50 +00:00
RegAllocLocal.cpp Use BitVector instead of vector<bool> which can be extremely slow. 2007-02-15 05:59:24 +00:00
RegAllocSimple.cpp Eliminate static ctors from Statistics 2006-12-19 22:41:21 +00:00
RegisterScavenging.cpp Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to 2007-03-26 22:23:54 +00:00
TwoAddressInstructionPass.cpp Keep UsedBlocks info accurate. 2007-03-18 09:02:31 +00:00
UnreachableBlockElim.cpp eliminate RegisterOpt. It does the same thing as RegisterPass. 2006-08-27 22:42:52 +00:00
VirtRegMap.cpp Don't call getOperandConstraint() if operand index is greater than 2007-03-27 00:48:28 +00:00
VirtRegMap.h First cut trivial re-materialization support. 2007-03-20 08:13:50 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

	mul lr, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	ldr r4, [sp, #+52]
	mla r4, r3, lr, r4

can be:

	mul lr, r4, lr
        mov r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

and then "merge" mul and mov:

	mul r4, r4, lr
	str lr, [sp, #+52]
	ldr lr, [r1, #+32]
	sxth r3, r3
	mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.