Hal Finkel 01f99d29c3 Use multiple virtual registers in PPC CR spilling ... Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-26 18:57:22 +00:00
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Analysis	BasicAA: Only query twice if the result of the more general query was MayAlias	2013-03-26 18:07:53 +00:00
Archive
AsmParser
Bitcode
CodeGen	Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings	2013-03-26 18:56:54 +00:00
DebugInfo	Fix missing std::. Not sure how this compiles for anyone else.	2013-03-21 00:57:21 +00:00
ExecutionEngine
IR	Swap the DIFile in DILexicalBlockFile out for the raw name/directory pair	2013-03-22 20:18:46 +00:00
IRReader	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00
Linker
MC
Object
Option
Support	Add missing file to cmake build.	2013-03-26 01:29:15 +00:00
TableGen	Allow TableGen DAG arguments to be just a name.	2013-03-24 19:36:51 +00:00
Target	Use multiple virtual registers in PPC CR spilling	2013-03-26 18:57:22 +00:00
Transforms	Make InstCombineCasts.cpp:OptimizeIntToFloatBitCast endian safe.	2013-03-26 15:36:14 +00:00
CMakeLists.txt	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00
LLVMBuild.txt	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00
Makefile	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00