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https://github.com/c64scene-ar/llvm-6502.git
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2f820a5d64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162736 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.1 KiB
LLVM
49 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse41,-avx < %s | FileCheck %s --check-prefix SSE41
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix AVX
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define i32 @veccond(<4 x i32> %input) {
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block: ; preds = %entry
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ret i32 0
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endif-block: ; preds = %entry,
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ret i32 1
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; SSE41: veccond
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; SSE41: ptest
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; SSE41: ret
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; AVX: veccond
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; AVX: vptest
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; AVX: ret
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}
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define i32 @vectest(<4 x i32> %input) {
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, 0
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%2 = zext i1 %1 to i32
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ret i32 %2
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; SSE41: vectest
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; SSE41: ptest
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; SSE41: ret
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; AVX: vectest
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; AVX: vptest
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; AVX: ret
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}
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define i32 @vecsel(<4 x i32> %input, i32 %a, i32 %b) {
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, 0
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%2 = select i1 %1, i32 %a, i32 %b
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ret i32 %2
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; SSE41: vecsel
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; SSE41: ptest
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; SSE41: ret
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; AVX: vecsel
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; AVX: vptest
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; AVX: ret
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}
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