Evan Cheng 020f4106f8 Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1

Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 20:00:08 +00:00
2011-12-12 21:14:40 +00:00
2011-12-12 13:06:25 +00:00
2011-12-12 21:14:40 +00:00
2011-12-12 21:14:40 +00:00
2011-06-12 15:26:54 +00:00
2011-11-22 20:05:48 +00:00

Low Level Virtual Machine (LLVM)
================================

This directory and its subdirectories contain source code for the Low Level
Virtual Machine, a toolkit for the construction of highly optimized compilers,
optimizers, and runtime environments.

LLVM is open source software. You may freely distribute it under the terms of
the license agreement found in LICENSE.txt.

Please see the HTML documentation provided in docs/index.html for further
assistance with LLVM.

If you're writing a package for LLVM, see docs/Packaging.html for our
suggestions.
Description
LLVM backend for 6502
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