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ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
5.4 KiB
C++
160 lines
5.4 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/IntrinsicLowering.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineImpls.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Transforms/Scalar.h"
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#include "Support/CommandLine.h"
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#include "Support/Statistic.h"
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using namespace llvm;
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namespace {
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cl::opt<bool> PrintCode("print-machineinstrs",
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cl::desc("Print generated machine code"));
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cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
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cl::desc("Use the 'simple' X86 instruction selector"));
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cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
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cl::desc("Disable the ssa-based peephole optimizer "
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"(defaults to disabled)"));
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cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
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cl::desc("Disable the X86 asm printer, for use "
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"when profiling the code generator."));
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}
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// allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the X86 backend.
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//
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TargetMachine *llvm::allocateX86TargetMachine(const Module &M,
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IntrinsicLowering *IL) {
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return new X86TargetMachine(M, IL);
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}
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/// X86TargetMachine ctor - Create an ILP32 architecture model
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///
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X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
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: TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4),
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JITInfo(*this) {
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}
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// addPassesToEmitAssembly - We currently use all of the same passes as the JIT
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// does to emit statically compiled machine code.
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bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: The code generator does not properly handle functions with
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// unreachable basic blocks.
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PM.add(createCFGSimplificationPass());
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if (NoPatternISel)
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PM.add(createX86SimpleInstructionSelector(*this));
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else
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PM.add(createX86PatternInstructionSelector(*this));
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// Run optional SSA-based machine code optimizations next...
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if (!NoSSAPeephole)
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PM.add(createX86SSAPeepholeOptimizerPass());
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// Print the instruction selected machine code...
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createX86FloatingPointStackifierPass());
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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if (PrintCode) // Print the register-allocated code
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PM.add(createX86CodePrinterPass(std::cerr, *this));
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if (!DisableOutput)
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PM.add(createX86CodePrinterPass(Out, *this));
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return false; // success!
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this is
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/// not supported for this target.
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///
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void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: The code generator does not properly handle functions with
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// unreachable basic blocks.
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PM.add(createCFGSimplificationPass());
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if (NoPatternISel)
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PM.add(createX86SimpleInstructionSelector(TM));
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else
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PM.add(createX86PatternInstructionSelector(TM));
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// Run optional SSA-based machine code optimizations next...
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if (!NoSSAPeephole)
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PM.add(createX86SSAPeepholeOptimizerPass());
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// FIXME: Add SSA based peephole optimizer here.
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// Print the instruction selected machine code...
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createX86FloatingPointStackifierPass());
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if (PrintCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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PM.add(createX86PeepholeOptimizerPass());
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if (PrintCode) // Print the register-allocated code
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PM.add(createX86CodePrinterPass(std::cerr, TM));
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}
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