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c3648ce2dc
Following the lead set by r209324, I'm making these tests match the whole instruction, so we can be sure we're lowering them correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209947 91177308-0d34-0410-b5e6-96231b3b80d8
203 lines
7.1 KiB
LLVM
203 lines
7.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; AVX128 tests:
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;CHECK-LABEL: vsel_float:
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; select mask is <i1 true, i1 false, i1 true, i1 false>.
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; Big endian representation is 0101 = 5.
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; '1' means takes the first argument, '0' means takes the second argument.
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; This is the opposite of the intel syntax, thus we expect
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; the inverted mask: 1010 = 10.
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; According to the ABI:
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; v1 is in xmm0 => first argument is xmm0.
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; v2 is in xmm1 => second argument is xmm1.
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; result is in xmm0 => destination argument.
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;CHECK: vblendps $10, %xmm1, %xmm0, %xmm0
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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;CHECK-LABEL: vsel_i32:
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;CHECK: vblendps $10, %xmm1, %xmm0, %xmm0
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;CHECK: ret
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define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2
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ret <4 x i32> %vsel
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}
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;CHECK-LABEL: vsel_double:
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;CHECK: vmovsd
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;CHECK: ret
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define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
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ret <2 x double> %vsel
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}
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;CHECK-LABEL: vsel_i64:
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;CHECK: vmovsd
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;CHECK: ret
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define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
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ret <2 x i64> %vsel
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}
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;CHECK-LABEL: vsel_i8:
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;CHECK: vpblendvb
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;CHECK: ret
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define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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%vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
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ret <16 x i8> %vsel
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}
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; AVX256 tests:
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;CHECK-LABEL: vsel_float8:
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;CHECK-NOT: vinsertf128
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; <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>
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; which translates into the boolean mask (big endian representation):
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; 00010001 = 17.
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; '1' means takes the first argument, '0' means takes the second argument.
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; This is the opposite of the intel syntax, thus we expect
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; the inverted mask: 11101110 = 238.
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;CHECK: vblendps $238, %ymm1, %ymm0, %ymm0
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;CHECK: ret
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define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
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ret <8 x float> %vsel
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}
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;CHECK-LABEL: vsel_i328:
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;CHECK-NOT: vinsertf128
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;CHECK: vblendps $238, %ymm1, %ymm0, %ymm0
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;CHECK-NEXT: ret
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define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
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ret <8 x i32> %vsel
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}
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;CHECK-LABEL: vsel_double8:
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; select mask is 2x: 0001 => intel mask: ~0001 = 14
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; ABI:
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; v1 is in ymm0 and ymm1.
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; v2 is in ymm2 and ymm3.
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; result is in ymm0 and ymm1.
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; Compute the low part: res.low = blend v1.low, v2.low, blendmask
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;CHECK: vblendpd $14, %ymm2, %ymm0, %ymm0
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; Compute the high part.
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;CHECK: vblendpd $14, %ymm3, %ymm1, %ymm1
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;CHECK: ret
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define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
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ret <8 x double> %vsel
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}
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;CHECK-LABEL: vsel_i648:
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;CHECK: vblendpd $14, %ymm2, %ymm0, %ymm0
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;CHECK: vblendpd $14, %ymm3, %ymm1, %ymm1
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;CHECK: ret
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define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
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ret <8 x i64> %vsel
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}
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;CHECK-LABEL: vsel_double4:
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;CHECK-NOT: vinsertf128
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;CHECK: vshufpd $10
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;CHECK-NEXT: ret
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define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v1, <4 x double> %v2
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ret <4 x double> %vsel
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}
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;; TEST blend + compares
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; CHECK: testa
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define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
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; CHECK: vcmplepd
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; CHECK: vblendvpd
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%max_is_x = fcmp oge <2 x double> %x, %y
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%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %max
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}
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; CHECK: testb
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define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
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; CHECK: vcmpnlepd
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; CHECK: vblendvpd
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%min_is_x = fcmp ult <2 x double> %x, %y
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %min
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}
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; If we can figure out a blend has a constant mask, we should emit the
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; blend instruction with an immediate mask
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define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
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; CHECK-LABEL: constant_blendvpd_avx:
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; CHECK-NOT: mov
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; CHECK: vblendpd
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; CHECK: ret
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %xy, <4 x double> %ab
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ret <4 x double> %1
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}
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define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {
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; CHECK-LABEL: constant_blendvps_avx:
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; CHECK-NOT: mov
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; CHECK: vblendps
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; CHECK: ret
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x float> %xyzw, <8 x float> %abcd
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ret <8 x float> %1
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}
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declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
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declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
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;; 4 tests for shufflevectors that optimize to blend + immediate
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; CHECK-LABEL: @blend_shufflevector_4xfloat
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define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) {
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; Equivalent select mask is <i1 true, i1 false, i1 true, i1 false>.
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; Big endian representation is 0101 = 5.
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; '1' means takes the first argument, '0' means takes the second argument.
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; This is the opposite of the intel syntax, thus we expect
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; Inverted mask: 1010 = 10.
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; According to the ABI:
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; a is in xmm0 => first argument is xmm0.
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; b is in xmm1 => second argument is xmm1.
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; Result is in xmm0 => destination argument.
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; CHECK: vblendps $10, %xmm1, %xmm0, %xmm0
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; CHECK: ret
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%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %1
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}
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; CHECK-LABEL: @blend_shufflevector_8xfloat
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define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) {
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; CHECK: vblendps $190, %ymm1, %ymm0, %ymm0
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; CHECK: ret
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%1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 6, i32 15>
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ret <8 x float> %1
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}
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; CHECK-LABEL: @blend_shufflevector_4xdouble
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define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) {
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; CHECK: vblendpd $2, %ymm1, %ymm0, %ymm0
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; CHECK: ret
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%1 = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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ret <4 x double> %1
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}
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; CHECK-LABEL: @blend_shufflevector_4xi64
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define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) {
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; CHECK: vblendpd $13, %ymm1, %ymm0, %ymm0
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; CHECK: ret
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%1 = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
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ret <4 x i64> %1
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}
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