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08f6677a7f
The i8 type is not registered with any register class. This causes a segmentation fault in MachineLICM::getRegisterClassIDAndCost. The code selects the first type associated with register class FPR8, which happens to be i8. It uses this type (i8) to get the representative class pointer, which is 0. It then uses this pointer to access a field, resulting in segmentation fault. Since i8 type is not being used for printing any neon instruction we can safely remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200046 91177308-0d34-0410-b5e6-96231b3b80d8
291 lines
11 KiB
TableGen
291 lines
11 KiB
TableGen
//===- AArch64RegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains declarations that describe the AArch64 register file
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//
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//===----------------------------------------------------------------------===//
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let Namespace = "AArch64" in {
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def sub_128 : SubRegIndex<128>;
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def sub_64 : SubRegIndex<64>;
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def sub_32 : SubRegIndex<32>;
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def sub_16 : SubRegIndex<16>;
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def sub_8 : SubRegIndex<8>;
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// Note: Code depends on these having consecutive numbers.
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def qqsub : SubRegIndex<256, 256>;
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def qsub_0 : SubRegIndex<128>;
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def qsub_1 : SubRegIndex<128, 128>;
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def qsub_2 : ComposedSubRegIndex<qqsub, qsub_0>;
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def qsub_3 : ComposedSubRegIndex<qqsub, qsub_1>;
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def dsub_0 : SubRegIndex<64>;
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def dsub_1 : SubRegIndex<64, 64>;
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def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
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def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
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}
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// Registers are identified with 5-bit ID numbers.
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class AArch64Reg<bits<16> enc, string n> : Register<n> {
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let HWEncoding = enc;
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let Namespace = "AArch64";
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}
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class AArch64RegWithSubs<bits<16> enc, string n, list<Register> subregs = [],
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list<SubRegIndex> inds = []>
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: AArch64Reg<enc, n> {
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let SubRegs = subregs;
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let SubRegIndices = inds;
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}
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//===----------------------------------------------------------------------===//
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// Integer registers: w0-w30, wzr, wsp, x0-x30, xzr, sp
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//===----------------------------------------------------------------------===//
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foreach Index = 0-30 in {
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def W#Index : AArch64Reg< Index, "w"#Index>, DwarfRegNum<[Index]>;
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}
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def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
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def WZR : AArch64Reg<31, "wzr">;
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// Could be combined with previous loop, but this way leaves w and x registers
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// consecutive as LLVM register numbers, which makes for easier debugging.
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foreach Index = 0-30 in {
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def X#Index : AArch64RegWithSubs<Index, "x"#Index,
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[!cast<Register>("W"#Index)], [sub_32]>,
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DwarfRegNum<[Index]>;
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}
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def XSP : AArch64RegWithSubs<31, "sp", [WSP], [sub_32]>, DwarfRegNum<[31]>;
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def XZR : AArch64RegWithSubs<31, "xzr", [WZR], [sub_32]>;
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// Most instructions treat register 31 as zero for reads and a black-hole for
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// writes.
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// Note that the order of registers is important for the Disassembler here:
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// tablegen uses it to form MCRegisterClass::getRegister, which we assume can
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// take an encoding value.
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def GPR32 : RegisterClass<"AArch64", [i32], 32,
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(add (sequence "W%u", 0, 30), WZR)> {
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}
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def GPR64 : RegisterClass<"AArch64", [i64], 64,
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(add (sequence "X%u", 0, 30), XZR)> {
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}
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def GPR32nowzr : RegisterClass<"AArch64", [i32], 32,
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(sequence "W%u", 0, 30)> {
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}
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def GPR64noxzr : RegisterClass<"AArch64", [i64], 64,
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(sequence "X%u", 0, 30)> {
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}
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// For tail calls, we can't use callee-saved registers or the structure-return
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// register, as they are supposed to be live across function calls and may be
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// clobbered by the epilogue.
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def tcGPR64 : RegisterClass<"AArch64", [i64], 64,
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(add (sequence "X%u", 0, 7),
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(sequence "X%u", 9, 18))> {
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}
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// Certain addressing-useful instructions accept sp directly. Again the order of
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// registers is important to the Disassembler.
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def GPR32wsp : RegisterClass<"AArch64", [i32], 32,
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(add (sequence "W%u", 0, 30), WSP)> {
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}
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def GPR64xsp : RegisterClass<"AArch64", [i64], 64,
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(add (sequence "X%u", 0, 30), XSP)> {
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}
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// Some aliases *only* apply to SP (e.g. MOV uses different encoding for SP and
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// non-SP variants). We can't use a bare register in those patterns because
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// TableGen doesn't like it, so we need a class containing just stack registers
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def Rxsp : RegisterClass<"AArch64", [i64], 64,
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(add XSP)> {
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}
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def Rwsp : RegisterClass<"AArch64", [i32], 32,
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(add WSP)> {
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}
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//===----------------------------------------------------------------------===//
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// Scalar registers in the vector unit:
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// b0-b31, h0-h31, s0-s31, d0-d31, q0-q31
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//===----------------------------------------------------------------------===//
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foreach Index = 0-31 in {
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def B # Index : AArch64Reg< Index, "b" # Index>,
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DwarfRegNum<[!add(Index, 64)]>;
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def H # Index : AArch64RegWithSubs<Index, "h" # Index,
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[!cast<Register>("B" # Index)], [sub_8]>,
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DwarfRegNum<[!add(Index, 64)]>;
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def S # Index : AArch64RegWithSubs<Index, "s" # Index,
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[!cast<Register>("H" # Index)], [sub_16]>,
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DwarfRegNum<[!add(Index, 64)]>;
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def D # Index : AArch64RegWithSubs<Index, "d" # Index,
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[!cast<Register>("S" # Index)], [sub_32]>,
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DwarfRegNum<[!add(Index, 64)]>;
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def Q # Index : AArch64RegWithSubs<Index, "q" # Index,
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[!cast<Register>("D" # Index)], [sub_64]>,
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DwarfRegNum<[!add(Index, 64)]>;
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}
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def FPR8 : RegisterClass<"AArch64", [v1i8], 8,
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(sequence "B%u", 0, 31)> {
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}
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def FPR16 : RegisterClass<"AArch64", [f16, v1i16], 16,
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(sequence "H%u", 0, 31)> {
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}
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def FPR32 : RegisterClass<"AArch64", [f32, v1i32], 32,
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(sequence "S%u", 0, 31)> {
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}
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def FPR64 : RegisterClass<"AArch64",
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[f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
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64, (sequence "D%u", 0, 31)>;
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def FPR128 : RegisterClass<"AArch64",
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[f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
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128, (sequence "Q%u", 0, 31)>;
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def FPR64Lo : RegisterClass<"AArch64",
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[f64, v2f32, v2i32, v4i16, v8i8, v1i64, v1f64],
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64, (sequence "D%u", 0, 15)>;
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def FPR128Lo : RegisterClass<"AArch64",
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[f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
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128, (sequence "Q%u", 0, 15)>;
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//===----------------------------------------------------------------------===//
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// Vector registers:
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//===----------------------------------------------------------------------===//
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def VPR64AsmOperand : AsmOperandClass {
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let Name = "VPR";
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let PredicateMethod = "isReg";
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let RenderMethod = "addRegOperands";
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}
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def VPR64 : RegisterOperand<FPR64, "printVPRRegister">;
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def VPR128 : RegisterOperand<FPR128, "printVPRRegister">;
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def VPR64Lo : RegisterOperand<FPR64Lo, "printVPRRegister">;
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def VPR128Lo : RegisterOperand<FPR128Lo, "printVPRRegister">;
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// Flags register
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def NZCV : Register<"nzcv"> {
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let Namespace = "AArch64";
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}
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def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
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let CopyCost = -1;
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let isAllocatable = 0;
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}
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//===----------------------------------------------------------------------===//
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// Consecutive vector registers
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//===----------------------------------------------------------------------===//
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// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D31_D0
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def Tuples2D : RegisterTuples<[dsub_0, dsub_1],
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[(rotl FPR64, 0), (rotl FPR64, 1)]>;
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// 3 Consecutive 64-bit registers: D0_D1_D2, ..., D31_D0_D1
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def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
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[(rotl FPR64, 0), (rotl FPR64, 1),
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(rotl FPR64, 2)]>;
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// 4 Consecutive 64-bit registers: D0_D1_D2_D3, ..., D31_D0_D1_D2
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def Tuples4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3],
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[(rotl FPR64, 0), (rotl FPR64, 1),
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(rotl FPR64, 2), (rotl FPR64, 3)]>;
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// 2 Consecutive 128-bit registers: Q0_Q1, Q1_Q2, ..., Q30_Q31
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def Tuples2Q : RegisterTuples<[qsub_0, qsub_1],
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[(rotl FPR128, 0), (rotl FPR128, 1)]>;
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// 3 Consecutive 128-bit registers: Q0_Q1_Q2, ..., Q31_Q0_Q1
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def Tuples3Q : RegisterTuples<[qsub_0, qsub_1, qsub_2],
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[(rotl FPR128, 0), (rotl FPR128, 1),
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(rotl FPR128, 2)]>;
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// 4 Consecutive 128-bit registers: Q0_Q1_Q2_Q3, ..., Q31_Q0_Q1_Q2
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def Tuples4Q : RegisterTuples<[qsub_0, qsub_1, qsub_2, qsub_3],
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[(rotl FPR128, 0), (rotl FPR128, 1),
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(rotl FPR128, 2), (rotl FPR128, 3)]>;
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// The followings are super register classes to model 2/3/4 consecutive
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// 64-bit/128-bit registers.
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def DPair : RegisterClass<"AArch64", [v2i64], 64, (add Tuples2D)>;
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def DTriple : RegisterClass<"AArch64", [untyped], 64, (add Tuples3D)> {
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let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
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}
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def DQuad : RegisterClass<"AArch64", [v4i64], 64, (add Tuples4D)>;
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def QPair : RegisterClass<"AArch64", [v4i64], 128, (add Tuples2Q)>;
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def QTriple : RegisterClass<"AArch64", [untyped], 128, (add Tuples3Q)> {
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let Size = 384; // 3 x 128 bits, we have no predefined type of that size.
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}
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def QQuad : RegisterClass<"AArch64", [v8i64], 128, (add Tuples4Q)>;
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// The followings are vector list operands
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multiclass VectorList_operands<string PREFIX, string LAYOUT, int Count,
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RegisterClass RegList> {
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def _asmoperand : AsmOperandClass {
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let Name = PREFIX # LAYOUT # Count;
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let RenderMethod = "addVectorListOperands";
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let PredicateMethod =
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"isVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">";
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let ParserMethod = "ParseVectorList";
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}
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def _operand : RegisterOperand<RegList,
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"printVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">"> {
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let ParserMatchClass =
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!cast<AsmOperandClass>(PREFIX # LAYOUT # "_asmoperand");
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}
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}
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multiclass VectorList_BHSD<string PREFIX, int Count, RegisterClass DRegList,
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RegisterClass QRegList> {
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defm 8B : VectorList_operands<PREFIX, "8B", Count, DRegList>;
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defm 4H : VectorList_operands<PREFIX, "4H", Count, DRegList>;
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defm 2S : VectorList_operands<PREFIX, "2S", Count, DRegList>;
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defm 1D : VectorList_operands<PREFIX, "1D", Count, DRegList>;
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defm 16B : VectorList_operands<PREFIX, "16B", Count, QRegList>;
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defm 8H : VectorList_operands<PREFIX, "8H", Count, QRegList>;
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defm 4S : VectorList_operands<PREFIX, "4S", Count, QRegList>;
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defm 2D : VectorList_operands<PREFIX, "2D", Count, QRegList>;
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}
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// Vector list operand with 1/2/3/4 registers: VOne8B_operand,..., VQuad2D_operand
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defm VOne : VectorList_BHSD<"VOne", 1, FPR64, FPR128>;
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defm VPair : VectorList_BHSD<"VPair", 2, DPair, QPair>;
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defm VTriple : VectorList_BHSD<"VTriple", 3, DTriple, QTriple>;
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defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;
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