mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-27 13:29:50 +00:00
41400da31e
2. Parsing .word directive in MBlaze asm parser 3. Fixing hack where memory instructions reversed order of last two parameters 4. Fixing many improperly encoded instructions 5. Support parsing special instructions (MFS,MTS,etc.) 6. Removing unused functions from inst printer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118941 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
10 KiB
TableGen
225 lines
10 KiB
TableGen
//===- MBlazeInstrFPU.td - MBlaze FPU Instruction defs -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MBlaze profiles and nodes
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MBlaze Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Memory Access Instructions
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//===----------------------------------------------------------------------===//
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class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
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TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>;
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class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TB<op, (outs GPR:$dst), (ins memri:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IILoad>;
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class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
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TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(OpNode (f32 GPR:$dst), xaddr:$addr)], IIStore>;
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class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TB<op, (outs), (ins GPR:$dst, memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(OpNode (f32 GPR:$dst), iaddr:$addr)], IIStore>;
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class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
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InstrItinClass itin> :
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TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
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class CmpFN<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], itin>;
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class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
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InstrItinClass itin> :
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TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
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!strconcat(instr_asm, " $dst, $c, $b"),
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[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
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class LogicF<bits<6> op, string instr_asm> :
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TB<op, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], IIAlu>;
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class LogicFI<bits<6> op, string instr_asm> :
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TB<op, (outs GPR:$dst), (ins GPR:$b, fimm:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], IIAlu>;
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let rb=0 in {
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class ArithF2<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[], itin>;
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class ArithIF<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[], itin>;
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class ArithFI<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TA<op, flags, (outs GPR:$dst), (ins GPR:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[], itin>;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FPU Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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let Predicates=[HasFPU] in {
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def FORI : LogicFI<0x28, "ori ">;
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def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIAlu>;
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def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIAlu>;
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def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIAlu>;
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def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIAlu>;
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}
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let Predicates=[HasFPU], isCodeGenOnly=1 in {
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def LWF : LoadFM<0x32, "lw ", load>;
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def LWFI : LoadFMI<0x3A, "lwi ", load>;
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def SWF : StoreFM<0x36, "sw ", store>;
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def SWFI : StoreFMI<0x3E, "swi ", store>;
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}
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let Predicates=[HasFPU,HasSqrt] in {
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def FLT : ArithIF<0x16, 0x280, "flt ", IIAlu>;
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def FINT : ArithFI<0x16, 0x300, "fint ", IIAlu>;
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def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIAlu>;
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}
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let isAsCheapAsAMove = 1 in {
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def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIAlu>;
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def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIAlu>;
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def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIAlu>;
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def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIAlu>;
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def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIAlu>;
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def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIAlu>;
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def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIAlu>;
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}
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let usesCustomInserter = 1 in {
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def Select_FCC : MBlazePseudo<(outs GPR:$dst),
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(ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC),
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"; SELECT_FCC PSEUDO!",
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[]>;
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}
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// Floating point conversions
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let Predicates=[HasFPU] in {
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def : Pat<(sint_to_fp GPR:$V), (FLT GPR:$V)>;
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def : Pat<(fp_to_sint GPR:$V), (FINT GPR:$V)>;
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def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>;
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}
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// SET_CC operations
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let Predicates=[HasFPU] in {
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_EQ GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_EQ GPR:$L, GPR:$R), 1)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_EQ GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(XOR (FCMP_UN GPR:$L, GPR:$R),
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(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(OR (FCMP_UN GPR:$L, GPR:$R),
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(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_GT GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_LT GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_GE GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_LE GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_GT GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLT),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_LT GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_GE GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_LE GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUEQ),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(OR (FCMP_UN GPR:$L, GPR:$R),
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(FCMP_EQ GPR:$L, GPR:$R)), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUNE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_NE GPR:$L, GPR:$R), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(OR (FCMP_UN GPR:$L, GPR:$R),
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(FCMP_GT GPR:$L, GPR:$R)), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(OR (FCMP_UN GPR:$L, GPR:$R),
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(FCMP_LT GPR:$L, GPR:$R)), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(OR (FCMP_UN GPR:$L, GPR:$R),
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(FCMP_GE GPR:$L, GPR:$R)), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(OR (FCMP_UN GPR:$L, GPR:$R),
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(FCMP_LE GPR:$L, GPR:$R)), 2)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_UN GPR:$L, GPR:$R), 1)>;
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def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUO),
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(Select_CC (ADDI (i32 R0), 1), (ADDI (i32 R0), 0),
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(FCMP_UN GPR:$L, GPR:$R), 2)>;
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}
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// SELECT operations
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def : Pat<(select (i32 GPR:$C), (f32 GPR:$T), (f32 GPR:$F)),
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(Select_FCC GPR:$T, GPR:$F, GPR:$C, 2)>;
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//===----------------------------------------------------------------------===//
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// Patterns for Floating Point Instructions
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//===----------------------------------------------------------------------===//
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def : Pat<(f32 fpimm:$imm), (FORI (i32 R0), fpimm:$imm)>;
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