Daniel Sanders 028e4d27b1 Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too ... Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-11 17:23:41 +00:00
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AArch64	Implement AArch64 Neon instruction set Perm.	2013-11-06 03:35:27 +00:00
ARM	[VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when setting	2013-11-08 18:14:17 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too	2013-11-11 17:23:41 +00:00
MSP430
NVPTX
PowerPC	Add PPC option for full register names in asm	2013-11-11 14:58:40 +00:00
R600	R600: Fix LowerUDIVREM	2013-11-06 17:36:04 +00:00
SPARC	[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.	2013-11-03 12:28:40 +00:00
SystemZ	[SystemZ] Automatically detect zEC12 and z196 hosts	2013-10-31 12:14:17 +00:00
Thumb
Thumb2
X86	[Stackmap] Materialize the jump address within the patchpoint noop slide.	2013-11-09 01:51:33 +00:00
XCore