llvm-6502/test/CodeGen
Justin Holewinski 0292a66bb1 [NVPTX] Handle addrspacecast constant expressions in aggregate initializers
We need to track if an AddrSpaceCast expression was seen when
generating an MCExpr for a ConstantExpr.  This change introduces a
custom lowerConstant method to the NVPTX asm printer that will create
NVPTXGenericMCSymbolRefExpr nodes at the appropriate places to encode
the information that a given symbol needs to be casted to a generic
address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236000 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-28 17:18:30 +00:00
..
AArch64 [AArch64] Also combine vector selects fed by non-i1 SETCCs. 2015-04-27 21:43:12 +00:00
ARM Switch lowering: Take branch weight into account when ordering for fall-through 2015-04-27 23:35:22 +00:00
BPF
CPP
Generic Switch lowering: Take branch weight into account when ordering for fall-through 2015-04-27 23:35:22 +00:00
Hexagon [Hexagon] Use constant extenders to fix up hardware loops 2015-04-27 14:16:43 +00:00
Inputs
Mips Reapply "[mips][FastISel] Implement shift ops for Mips fast-isel."" 2015-04-27 13:28:05 +00:00
MSP430
NVPTX [NVPTX] Handle addrspacecast constant expressions in aggregate initializers 2015-04-28 17:18:30 +00:00
PowerPC [PPC64LE] Remove unnecessary swaps from lane-insensitive vector computations 2015-04-27 19:57:34 +00:00
R600
SPARC
SystemZ
Thumb
Thumb2
WinEH
X86 Fixed crash of variable shift inst on AVX2 2015-04-28 14:46:35 +00:00
XCore