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https://github.com/c64scene-ar/llvm-6502.git
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02a453074d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15363 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
2.5 KiB
C++
74 lines
2.5 KiB
C++
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "X86GenInstrInfo.inc"
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using namespace llvm;
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X86InstrInfo::X86InstrInfo()
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: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
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}
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bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
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oc == X86::FpMOV) {
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid register-register move instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
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MachineBasicBlock& TMBB) const {
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BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
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}
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MachineBasicBlock::iterator
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X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
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unsigned Opcode = MI->getOpcode();
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assert(isBranch(Opcode) && "MachineInstr must be a branch");
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unsigned ROpcode;
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switch (Opcode) {
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case X86::JB: ROpcode = X86::JAE;
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case X86::JAE: ROpcode = X86::JB;
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case X86::JE: ROpcode = X86::JNE;
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case X86::JNE: ROpcode = X86::JE;
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case X86::JBE: ROpcode = X86::JA;
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case X86::JA: ROpcode = X86::JBE;
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case X86::JS: ROpcode = X86::JNS;
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case X86::JNS: ROpcode = X86::JS;
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case X86::JL: ROpcode = X86::JGE;
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case X86::JGE: ROpcode = X86::JL;
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case X86::JLE: ROpcode = X86::JG;
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case X86::JG: ROpcode = X86::JLE;
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default:
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assert(0 && "Cannot reverse unconditional branches!");
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}
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MachineBasicBlock* MBB = MI->getParent();
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MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
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MachineInstrBuilder IB = BuildMI(*MBB, MBB->erase(MI), ROpcode, 1);
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IB.addMBB(TMBB);
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return IB;
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}
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