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https://github.com/c64scene-ar/llvm-6502.git
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140a58f9df
No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27536 91177308-0d34-0410-b5e6-96231b3b80d8
657 lines
32 KiB
TableGen
657 lines
32 KiB
TableGen
//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Altivec extension to the PowerPC instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Altivec transformation functions and pattern fragments.
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//
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/// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
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/// shuffle mask for the VPKUHUM or VPKUWUM instructions.
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def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVPKUHUMShuffleMask(N, false);
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}]>;
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def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVPKUWUMShuffleMask(N, false);
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}]>;
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def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVPKUHUMShuffleMask(N, true);
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}]>;
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def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVPKUWUMShuffleMask(N, true);
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}]>;
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def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 1, false);
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}]>;
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def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 2, false);
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}]>;
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def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 4, false);
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}]>;
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def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 1, false);
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}]>;
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def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 2, false);
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}]>;
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def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 4, false);
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}]>;
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def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 1, true);
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}]>;
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def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 2, true);
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}]>;
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def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGLShuffleMask(N, 4, true);
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}]>;
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def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 1, true);
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}]>;
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def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 2, true);
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}]>;
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def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVMRGHShuffleMask(N, 4, true);
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}]>;
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def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
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}]>;
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def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVSLDOIShuffleMask(N, false) != -1;
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}], VSLDOI_get_imm>;
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/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
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/// vector_shuffle(X,undef,mask) by the dag combiner.
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def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
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}]>;
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def VSLDOI_unary_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isVSLDOIShuffleMask(N, true) != -1;
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}], VSLDOI_unary_get_imm>;
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// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
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def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::getVSPLTImmediate(N, 1));
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}]>;
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def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isSplatShuffleMask(N, 1);
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}], VSPLTB_get_imm>;
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def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::getVSPLTImmediate(N, 2));
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}]>;
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def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isSplatShuffleMask(N, 2);
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}], VSPLTH_get_imm>;
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def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
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return getI32Imm(PPC::getVSPLTImmediate(N, 4));
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}]>;
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def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
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return PPC::isSplatShuffleMask(N, 4);
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}], VSPLTW_get_imm>;
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// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
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def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
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return PPC::get_VSPLI_elt(N, 1, *CurDAG);
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}]>;
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def vecspltisb : PatLeaf<(build_vector), [{
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return PPC::get_VSPLI_elt(N, 1, *CurDAG).Val != 0;
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}], VSPLTISB_get_imm>;
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// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
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def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
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return PPC::get_VSPLI_elt(N, 2, *CurDAG);
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}]>;
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def vecspltish : PatLeaf<(build_vector), [{
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return PPC::get_VSPLI_elt(N, 2, *CurDAG).Val != 0;
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}], VSPLTISH_get_imm>;
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// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
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def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
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return PPC::get_VSPLI_elt(N, 4, *CurDAG);
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}]>;
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def vecspltisw : PatLeaf<(build_vector), [{
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return PPC::get_VSPLI_elt(N, 4, *CurDAG).Val != 0;
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}], VSPLTISW_get_imm>;
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//===----------------------------------------------------------------------===//
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// Helpers for defining instructions that directly correspond to intrinsics.
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// VA1a_Int - A VAForm_1a intrinsic definition.
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class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
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: VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
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!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
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// VX1_Int - A VXForm_1 intrinsic definition.
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class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
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: VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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!strconcat(opc, " $vD, $vA, $vB"), VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
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// VX2_Int - A VXForm_2 intrinsic definition.
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class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
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: VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
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!strconcat(opc, " $vD, $vB"), VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vB))]>;
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//===----------------------------------------------------------------------===//
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// Instruction Definitions.
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def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
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[(set VRRC:$rD, (v4f32 (undef)))]>;
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let noResults = 1 in {
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def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
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"dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
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def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
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"dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
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def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
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"dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
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}
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def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
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"mfvcr $vD", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
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def MTVSCR : VXForm_5<1604, (ops VRRC:$vB),
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"mtvcr $vB", LdStGeneral,
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[(int_ppc_altivec_mtvscr VRRC:$vB)]>;
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let isLoad = 1, PPC970_Unit = 2 in { // Loads.
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def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
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"lvebx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
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def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
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"lvehx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
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def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
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"lvewx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
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def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
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"lvx $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
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def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
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"lvxl $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
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}
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def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
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"lvsl $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
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PPC970_Unit_LSU;
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def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
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"lvsr $vD, $src", LdStGeneral,
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[(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
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PPC970_Unit_LSU;
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
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def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
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"stvebx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
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def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
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"stvehx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
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def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
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"stvewx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
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def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
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"stvx $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
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def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
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"stvxl $rS, $dst", LdStGeneral,
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[(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
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}
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let PPC970_Unit = 5 in { // VALU Operations.
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// VA-Form instructions. 3-input AltiVec ops.
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def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vmaddfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB))]>,
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Requires<[FPContractions]>;
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def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
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"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
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[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
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VRRC:$vB)))]>,
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Requires<[FPContractions]>;
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def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
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def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
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def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>;
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def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
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def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
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// Shuffles.
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def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
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"vsldoi $vD, $vA, $vB, $SH", VecFP,
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[(set VRRC:$vD,
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(vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
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VSLDOI_shuffle_mask:$SH))]>;
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// VX-Form instructions. AltiVec arithmetic ops.
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def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddfp $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
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def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vaddubm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
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def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduhm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
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def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vadduwm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
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def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
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def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
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def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
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def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
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def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
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def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
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def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vand $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vandc $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
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def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfsx $vD, $vB, $UIMM", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
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def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vcfux $vD, $vB, $UIMM", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
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def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vctsxs $vD, $vB, $UIMM", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
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def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vctuxs $vD, $vB, $UIMM", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
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def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
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def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
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def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
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def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
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def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
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def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
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def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
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def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
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def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
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def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
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def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
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def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
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def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
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def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
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def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
|
|
def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
|
|
def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
|
|
def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
|
|
def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>;
|
|
def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
|
|
def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
|
|
def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
|
|
|
|
def VMRGHB : VXForm_1< 12, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vmrghb $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VMRGHB_shuffle_mask))]>;
|
|
def VMRGHH : VXForm_1< 76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vmrghh $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VMRGHH_shuffle_mask))]>;
|
|
def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vmrghw $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VMRGHW_shuffle_mask))]>;
|
|
def VMRGLB : VXForm_1<268, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vmrglb $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VMRGLB_shuffle_mask))]>;
|
|
def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vmrglh $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VMRGLH_shuffle_mask))]>;
|
|
def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vmrglw $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VMRGLW_shuffle_mask))]>;
|
|
|
|
def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
|
|
def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
|
|
def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
|
|
def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
|
|
def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
|
|
def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
|
|
|
|
def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
|
|
def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
|
|
def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
|
|
def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
|
|
def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
|
|
def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
|
|
def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
|
|
def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
|
|
|
|
def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
|
|
def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
|
|
def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
|
|
def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
|
|
def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
|
|
def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
|
|
|
|
def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
|
|
|
|
def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vsubfp $vD, $vA, $vB", VecGeneral,
|
|
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
|
|
def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vsububm $vD, $vA, $vB", VecGeneral,
|
|
[(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
|
|
def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vsubuhm $vD, $vA, $vB", VecGeneral,
|
|
[(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
|
|
def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vsubuwm $vD, $vA, $vB", VecGeneral,
|
|
[(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
|
|
|
|
def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
|
|
def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
|
|
def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
|
|
def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
|
|
def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
|
|
def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
|
|
def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
|
|
def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
|
|
def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
|
|
def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
|
|
def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
|
|
|
|
def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vnor $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
|
|
def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vor $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
|
|
def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vxor $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
|
|
|
|
def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
|
|
def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
|
|
def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
|
|
|
|
def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
|
|
def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
|
|
def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
|
|
def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
|
|
def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
|
|
|
|
def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
|
"vspltb $vD, $vB, $UIMM", VecPerm,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
|
|
VSPLTB_shuffle_mask:$UIMM))]>;
|
|
def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
|
"vsplth $vD, $vB, $UIMM", VecPerm,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
|
|
VSPLTH_shuffle_mask:$UIMM))]>;
|
|
def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
|
|
"vspltw $vD, $vB, $UIMM", VecPerm,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
|
|
VSPLTW_shuffle_mask:$UIMM))]>;
|
|
|
|
def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
|
|
def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
|
|
def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
|
|
def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
|
|
def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
|
|
def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
|
|
def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
|
|
def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
|
|
|
|
|
|
def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
|
|
"vspltisb $vD, $SIMM", VecPerm,
|
|
[(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
|
|
def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
|
|
"vspltish $vD, $SIMM", VecPerm,
|
|
[(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
|
|
def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
|
|
"vspltisw $vD, $SIMM", VecPerm,
|
|
[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
|
|
|
|
// Vector Pack.
|
|
def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
|
|
def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
|
|
def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
|
|
def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
|
|
def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
|
|
def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkuhum $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VPKUHUM_shuffle_mask))]>;
|
|
def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
|
|
def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
|
|
"vpkuwum $vD, $vA, $vB", VecFP,
|
|
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
|
VRRC:$vB, VPKUWUM_shuffle_mask))]>;
|
|
def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
|
|
|
|
// Vector Unpack.
|
|
def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
|
|
def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
|
|
def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
|
|
def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
|
|
def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
|
|
def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
|
|
|
|
|
|
// Altivec Comparisons.
|
|
|
|
class VCMP<bits<10> xo, string asmstr, ValueType Ty>
|
|
: VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
|
|
[(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
|
|
class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
|
|
: VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
|
|
[(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
|
|
let Defs = [CR6];
|
|
let RC = 1;
|
|
}
|
|
|
|
// f32 element comparisons.0
|
|
def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
|
|
def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
|
|
def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
|
|
def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
|
|
def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
|
|
|
|
// i8 element comparisons.
|
|
def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
|
|
def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
|
|
def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
|
|
def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
|
|
def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
|
|
def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
|
|
|
|
// i16 element comparisons.
|
|
def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
|
|
def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
|
|
def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
|
|
def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
|
|
def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
|
|
def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
|
|
|
|
// i32 element comparisons.
|
|
def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
|
|
def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
|
|
def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
|
|
def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
|
|
def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
|
|
def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
|
|
|
|
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
|
|
"vxor $vD, $vD, $vD", VecFP,
|
|
[(set VRRC:$vD, (v4f32 immAllZerosV))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Additional Altivec Patterns
|
|
//
|
|
|
|
// DS* intrinsics.
|
|
def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
|
|
def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
|
|
def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
|
|
(DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
|
|
def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
|
|
(DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
|
|
def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
|
|
(DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
|
|
def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
|
|
(DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
|
|
|
|
// Undef/Zero.
|
|
def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
|
|
def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
|
|
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
|
|
def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
|
|
def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
|
|
def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
|
|
|
|
// Loads.
|
|
def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
|
|
def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
|
|
def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
|
|
def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>;
|
|
|
|
// Stores.
|
|
def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
|
|
(STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
|
|
def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
|
|
(STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
|
|
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
|
|
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
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def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst),
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(STVX (v4f32 VRRC:$rS), xoaddr:$dst)>;
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// Bit conversions.
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def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
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def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
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// Shuffles.
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// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
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(VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
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(VPKUWUM VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
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(VPKUHUM VRRC:$vA, VRRC:$vA)>;
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// Match vmrg*(x,x)
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
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(VMRGLB VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
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(VMRGLH VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
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(VMRGLW VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
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(VMRGHB VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
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(VMRGHH VRRC:$vA, VRRC:$vA)>;
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def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
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(VMRGHW VRRC:$vA, VRRC:$vA)>;
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// Immediate vector formation with vsplti*.
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def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>;
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def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>;
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def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>;
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def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>;
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def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>;
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def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>;
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def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>;
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def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>;
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def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>;
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// Logical Operations
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def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>;
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def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>;
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def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>;
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def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>;
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def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>;
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def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>;
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def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>;
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def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>;
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def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>;
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def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>;
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def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>;
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def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))),
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(v16i8 (VANDC VRRC:$A, VRRC:$B))>;
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def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
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(v8i16 (VANDC VRRC:$A, VRRC:$B))>;
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def : Pat<(fmul VRRC:$vA, VRRC:$vB),
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(VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
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// Fused multiply add and multiply sub for packed float. These are represented
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// separately from the real instructions above, for operations that must have
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// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
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def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
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(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
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def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
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(v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
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