mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0b8c9a80f2
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
107 lines
3.5 KiB
C++
107 lines
3.5 KiB
C++
//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the PowerPC specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PPC_TARGETMACHINE_H
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#define PPC_TARGETMACHINE_H
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#include "PPCFrameLowering.h"
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#include "PPCISelLowering.h"
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#include "PPCInstrInfo.h"
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#include "PPCJITInfo.h"
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#include "PPCSelectionDAGInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetTransformImpl.h"
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namespace llvm {
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/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
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///
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class PPCTargetMachine : public LLVMTargetMachine {
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PPCSubtarget Subtarget;
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const DataLayout DL; // Calculates type size & alignment
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PPCInstrInfo InstrInfo;
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PPCFrameLowering FrameLowering;
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PPCJITInfo JITInfo;
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PPCTargetLowering TLInfo;
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PPCSelectionDAGInfo TSInfo;
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InstrItineraryData InstrItins;
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ScalarTargetTransformImpl STTI;
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VectorTargetTransformImpl VTTI;
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public:
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PPCTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool is64Bit);
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virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const PPCFrameLowering *getFrameLowering() const {
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return &FrameLowering;
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}
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virtual PPCJITInfo *getJITInfo() { return &JITInfo; }
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virtual const PPCTargetLowering *getTargetLowering() const {
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return &TLInfo;
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}
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virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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virtual const PPCRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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virtual const DataLayout *getDataLayout() const { return &DL; }
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virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; }
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virtual const InstrItineraryData *getInstrItineraryData() const {
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return &InstrItins;
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}
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virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
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return &STTI;
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}
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virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
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return &VTTI;
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}
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// Pass Pipeline Configuration
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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virtual bool addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE);
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};
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/// PPC32TargetMachine - PowerPC 32-bit target machine.
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///
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class PPC32TargetMachine : public PPCTargetMachine {
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virtual void anchor();
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public:
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PPC32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// PPC64TargetMachine - PowerPC 64-bit target machine.
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///
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class PPC64TargetMachine : public PPCTargetMachine {
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virtual void anchor();
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public:
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PPC64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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