mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c2884320fe
This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
217 lines
6.8 KiB
LLVM
217 lines
6.8 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
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@var32 = global i32 0
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@var64 = global i64 0
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define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
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; CHECK-LABEL: test_csel:
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%tst1 = icmp ugt i32 %lhs32, %rhs32
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%val1 = select i1 %tst1, i32 42, i32 52
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store i32 %val1, i32* @var32
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; CHECK-DAG: movz [[W52:w[0-9]+]], #52
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; CHECK-DAG: movz [[W42:w[0-9]+]], #42
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; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi
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%rhs64 = sext i32 %rhs32 to i64
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%tst2 = icmp sle i64 %lhs64, %rhs64
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%val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64
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store i64 %val2, i64* @var64
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; CHECK-DAG: cmp [[LHS:x[0-9]+]], [[RHS:w[0-9]+]], sxtw
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; CHECK-DAG: sxtw [[EXT_RHS:x[0-9]+]], [[RHS]]
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; CHECK: csel {{x[0-9]+}}, [[LHS]], [[EXT_RHS]], le
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ret void
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; CHECK: ret
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}
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define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
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; CHECK-LABEL: test_floatcsel:
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%tst1 = fcmp one float %lhs32, %rhs32
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; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
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; CHECK-NOFP-NOT: fcmp
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%val1 = select i1 %tst1, i32 42, i32 52
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store i32 %val1, i32* @var32
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; CHECK: movz [[W52:w[0-9]+]], #52
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; CHECK: movz [[W42:w[0-9]+]], #42
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; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi
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; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt
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%tst2 = fcmp ueq double %lhs64, %rhs64
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; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
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; CHECK-NOFP-NOT: fcmp
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%val2 = select i1 %tst2, i64 9, i64 15
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store i64 %val2, i64* @var64
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; CHECK: movz [[CONST15:x[0-9]+]], #15
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; CHECK: movz [[CONST9:x[0-9]+]], #9
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; CHECK: csel [[MAYBETRUE:x[0-9]+]], [[CONST9]], [[CONST15]], eq
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; CHECK: csel {{x[0-9]+}}, [[CONST9]], [[MAYBETRUE]], vs
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ret void
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; CHECK: ret
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}
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define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
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; CHECK-LABEL: test_csinc:
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; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
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%tst1 = icmp ugt i32 %lhs32, %rhs32
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%inc1 = add i32 %rhs32, 1
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%val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
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store volatile i32 %val1, i32* @var32
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; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
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; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls
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%rhs2 = add i32 %rhs32, 42
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%tst2 = icmp sle i32 %lhs32, %rhs2
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%inc2 = add i32 %rhs32, 1
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%val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
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store volatile i32 %val2, i32* @var32
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; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
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; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
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; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
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%rhs3 = sext i32 %rhs32 to i64
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%tst3 = icmp ugt i64 %lhs64, %rhs3
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%inc3 = add i64 %rhs3, 1
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%val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
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store volatile i64 %val3, i64* @var64
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; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
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; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
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%rhs4 = zext i32 %rhs32 to i64
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%tst4 = icmp sle i64 %lhs64, %rhs4
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%inc4 = add i64 %rhs4, 1
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%val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
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store volatile i64 %val4, i64* @var64
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; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
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; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
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ret void
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; CHECK: ret
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}
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define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
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; CHECK-LABEL: test_csinv:
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; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
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%tst1 = icmp ugt i32 %lhs32, %rhs32
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%inc1 = xor i32 -1, %rhs32
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%val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
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store volatile i32 %val1, i32* @var32
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; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
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; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
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%rhs2 = add i32 %rhs32, 42
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%tst2 = icmp sle i32 %lhs32, %rhs2
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%inc2 = xor i32 -1, %rhs32
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%val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
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store volatile i32 %val2, i32* @var32
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; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
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; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
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; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
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%rhs3 = sext i32 %rhs32 to i64
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%tst3 = icmp ugt i64 %lhs64, %rhs3
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%inc3 = xor i64 -1, %rhs3
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%val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
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store volatile i64 %val3, i64* @var64
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; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
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; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
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%rhs4 = zext i32 %rhs32 to i64
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%tst4 = icmp sle i64 %lhs64, %rhs4
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%inc4 = xor i64 -1, %rhs4
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%val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
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store volatile i64 %val4, i64* @var64
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; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
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; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
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ret void
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; CHECK: ret
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}
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define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
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; CHECK-LABEL: test_csneg:
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; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
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%tst1 = icmp ugt i32 %lhs32, %rhs32
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%inc1 = sub i32 0, %rhs32
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%val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
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store volatile i32 %val1, i32* @var32
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; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
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; CHECK: csneg {{w[0-9]+}}, [[LHS]], [[RHS]], ls
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%rhs2 = add i32 %rhs32, 42
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%tst2 = icmp sle i32 %lhs32, %rhs2
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%inc2 = sub i32 0, %rhs32
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%val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
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store volatile i32 %val2, i32* @var32
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; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
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; CHECK: csneg {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
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; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
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%rhs3 = sext i32 %rhs32 to i64
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%tst3 = icmp ugt i64 %lhs64, %rhs3
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%inc3 = sub i64 0, %rhs3
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%val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
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store volatile i64 %val3, i64* @var64
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; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
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; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
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%rhs4 = zext i32 %rhs32 to i64
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%tst4 = icmp sle i64 %lhs64, %rhs4
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%inc4 = sub i64 0, %rhs4
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%val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
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store volatile i64 %val4, i64* @var64
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; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
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; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
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ret void
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; CHECK: ret
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}
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define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
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; CHECK-LABEL: test_cset:
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; N.b. code is not optimal here (32-bit csinc would be better) but
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; incoming DAG is too complex
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%tst1 = icmp eq i32 %lhs, %rhs
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%val1 = zext i1 %tst1 to i32
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store i32 %val1, i32* @var32
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; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ne
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%rhs64 = sext i32 %rhs to i64
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%tst2 = icmp ule i64 %lhs64, %rhs64
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%val2 = zext i1 %tst2 to i64
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store i64 %val2, i64* @var64
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; CHECK: csinc {{w[0-9]+}}, wzr, wzr, hi
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ret void
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; CHECK: ret
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}
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define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
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; CHECK-LABEL: test_csetm:
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%tst1 = icmp eq i32 %lhs, %rhs
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%val1 = sext i1 %tst1 to i32
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store i32 %val1, i32* @var32
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; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: csinv {{w[0-9]+}}, wzr, wzr, ne
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%rhs64 = sext i32 %rhs to i64
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%tst2 = icmp ule i64 %lhs64, %rhs64
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%val2 = sext i1 %tst2 to i64
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store i64 %val2, i64* @var64
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; CHECK: csinv {{x[0-9]+}}, xzr, xzr, hi
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ret void
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; CHECK: ret
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}
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