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https://github.com/c64scene-ar/llvm-6502.git
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370981ad17
Summary: SLP Vectorization of intrinsics (r203707) has exposed cases where the expansion of vector bswap is failing (PR19151). Reviewers: hfinkel CC: chandlerc Differential Revision: http://llvm-reviews.chandlerc.com/D3104 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204163 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.4 KiB
LLVM
48 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
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; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 | FileCheck %s -check-prefix=mips16
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define i32 @bswap32(i32 %x) nounwind readnone {
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entry:
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; MIPS32-LABEL: bswap32:
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; MIPS32: wsbh $[[R0:[0-9]+]]
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; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
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; mips16: .ent bswap32
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%or.3 = call i32 @llvm.bswap.i32(i32 %x)
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ret i32 %or.3
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}
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define i64 @bswap64(i64 %x) nounwind readnone {
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entry:
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; MIPS64-LABEL: bswap64:
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; MIPS64: dsbh $[[R0:[0-9]+]]
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; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
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; mips16: .ent bswap64
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%or.7 = call i64 @llvm.bswap.i64(i64 %x)
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ret i64 %or.7
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}
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define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone {
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entry:
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; MIPS32-LABEL: bswapv4i32:
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; MIPS32: wsbh $[[R0:[0-9]+]]
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; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
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; MIPS32: wsbh $[[R0:[0-9]+]]
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; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
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; MIPS32: wsbh $[[R0:[0-9]+]]
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; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
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; MIPS32: wsbh $[[R0:[0-9]+]]
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; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
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; mips16: .ent bswapv4i32
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%ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x)
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ret <4 x i32> %ret
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}
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declare i32 @llvm.bswap.i32(i32) nounwind readnone
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declare i64 @llvm.bswap.i64(i64) nounwind readnone
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
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