mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
5a70dd1d82
Similar to gep (r230786) and load (r230794) changes.
Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.
(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)
import fileinput
import sys
import re
rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)
def conv(match):
line = match.group(1)
line += match.group(4)
line += ", "
line += match.group(2)
return line
line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
sys.stdout.write(line[off:match.start()])
sys.stdout.write(conv(match))
off = match.end()
sys.stdout.write(line[off:])
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
395 lines
15 KiB
LLVM
395 lines
15 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win64 | FileCheck %s
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; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
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; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
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; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
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; rdar://7304838
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; CodeGenPrepare should move the zext into the block with the load
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; so that SelectionDAG can select it with the load.
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;
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; CHECK-LABEL: foo:
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; CHECK: movsbl ({{%rdi|%rcx}}), %eax
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;
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; OPTALL-LABEL: @foo
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; OPTALL: store i32 [[ZEXT]], i32* %q
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; OPTALL: ret
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define void @foo(i8* %p, i32* %q) {
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entry:
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%t = load i8, i8* %p
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %t to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload is an operation with only one
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; argument to explicitly extend is in the the way.
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; OPTALL-LABEL: @promoteOneArg
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
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; Make sure the operation is not promoted when the promotion pass is disabled.
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], i32* %q
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; OPTALL: ret
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define void @promoteOneArg(i8* %p, i32* %q) {
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entry:
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%t = load i8, i8* %p
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%add = add nuw i8 %t, 2
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload is an operation with only one
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; argument to explicitly extend is in the the way.
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; Version with sext.
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; OPTALL-LABEL: @promoteOneArgSExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
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; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], i32* %q
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; OPTALL: ret
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define void @promoteOneArgSExt(i8* %p, i32* %q) {
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entry:
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%t = load i8, i8* %p
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%add = add nsw i8 %t, 2
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i8 %add to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload is an operation with two
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; arguments to explicitly extend is in the the way.
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; Extending %add will create two extensions:
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; 1. One for %b.
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; 2. One for %t.
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; #1 will not be removed as we do not know anything about %b.
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; #2 may not be merged with the load because %t is used in a comparison.
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; Since two extensions may be emitted in the end instead of one before the
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; transformation, the regular heuristic does not apply the optimization.
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;
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; OPTALL-LABEL: @promoteTwoArgZext
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
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;
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; OPTALL: store i32 [[RES]], i32* %q
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; OPTALL: ret
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define void @promoteTwoArgZext(i8* %p, i32* %q, i8 %b) {
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entry:
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%t = load i8, i8* %p
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%add = add nuw i8 %t, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload is an operation with two
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; arguments to explicitly extend is in the the way.
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; Version with sext.
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; OPTALL-LABEL: @promoteTwoArgSExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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;
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; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
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; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXTLD]], [[SEXTB]]
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;
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
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;
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], i32* %q
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; OPTALL: ret
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define void @promoteTwoArgSExt(i8* %p, i32* %q, i8 %b) {
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entry:
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%t = load i8, i8* %p
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%add = add nsw i8 %t, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i8 %add to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we do not a zextload if we need to introduce more than
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; one additional extension.
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; OPTALL-LABEL: @promoteThreeArgZext
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
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; STRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
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; STRESS-NEXT: [[ZEXTC:%[a-zA-Z_0-9-]+]] = zext i8 %c to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[TMP]], [[ZEXTC]]
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;
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; NONSTRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
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; NONSTRESS-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[TMP]], %c
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; DISABLE: add nuw i8
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; OPTALL: store i32 [[RES]], i32* %q
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; OPTALL: ret
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define void @promoteThreeArgZext(i8* %p, i32* %q, i8 %b, i8 %c) {
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entry:
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%t = load i8, i8* %p
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%tmp = add nuw i8 %t, %b
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%add = add nuw i8 %tmp, %c
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload after promoting and merging
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; two extensions.
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; OPTALL-LABEL: @promoteMergeExtArgZExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
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;
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; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
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;
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; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
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;
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; OPTALL: store i32 [[RES]], i32* %q
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; OPTALL: ret
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define void @promoteMergeExtArgZExt(i8* %p, i32* %q, i16 %b) {
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entry:
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%t = load i8, i8* %p
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%ext = zext i8 %t to i16
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%add = add nuw i16 %ext, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i16 %add to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload after promoting and merging
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; two extensions.
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; Version with sext.
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; OPTALL-LABEL: @promoteMergeExtArgSExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXTLD]], [[ZEXTB]]
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;
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; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
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;
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; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], i32* %q
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; OPTALL: ret
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define void @promoteMergeExtArgSExt(i8* %p, i32* %q, i16 %b) {
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entry:
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%t = load i8, i8* %p
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%ext = zext i8 %t to i16
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%add = add nsw i16 %ext, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i16 %add to i32
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store i32 %s, i32* %q
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ret void
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false:
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ret void
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}
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; Check that we manage to catch all the extload opportunities that are exposed
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; by the different iterations of codegen prepare.
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; Moreover, check that we do not promote more than we need to.
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; Here is what is happening in this test (not necessarly in this order):
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; 1. We try to promote the operand of %sextadd.
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; a. This creates one sext of %ld2 and one of %zextld
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; b. The sext of %ld2 can be combine with %ld2, so we remove one sext but
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; introduced one. This is fine with the current heuristic: neutral.
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; => We have one zext of %zextld left and we created one sext of %ld2.
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; 2. We try to promote the operand of %sextaddza.
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; a. This creates one sext of %zexta and one of %zextld
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; b. The sext of %zexta does not lead to any load, it stays here, even if it
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; could have been combine with the zext of %a.
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; c. The sext of %zextld leads to %ld and can be combined with it. This is
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; done by promoting %zextld. This is fine with the current heuristic:
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; neutral.
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; => We have created a new zext of %ld and we created one sext of %zexta.
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; 3. We try to promote the operand of %sextaddb.
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; a. This creates one sext of %b and one of %zextld
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; b. The sext of %b is a dead-end, nothing to be done.
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; c. Same thing as 2.c. happens.
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; => We have created a new zext of %ld and we created one sext of %b.
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; 4. We try to promote the operand of the zext of %zextld introduced in #1.
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; a. Same thing as 2.c. happens.
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; b. %zextld does not have any other uses. It is dead coded.
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; => We have created a new zext of %ld and we removed a zext of %zextld and
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; a zext of %ld.
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; Currently we do not try to reuse existing extensions, so in the end we have
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; 3 identical zext of %ld. The extensions will be CSE'ed by SDag.
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;
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; OPTALL-LABEL: @severalPromotions
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %addr1
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; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
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; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
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; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
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; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32, i32* %addr2
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; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64
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; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_1]]
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; We do not combine this one: see 2.b.
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; OPT-NEXT: [[ZEXTA:%[a-zA-Z_0-9-]+]] = zext i8 %a to i32
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; OPT-NEXT: [[SEXTZEXTA:%[a-zA-Z_0-9-]+]] = sext i32 [[ZEXTA]] to i64
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; OPT-NEXT: [[RESZA:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTZEXTA]], [[ZEXTLD1_3]]
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; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
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; OPT-NEXT: [[RESB:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTB]], [[ZEXTLD1_2]]
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;
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
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; DISABLE: [[ADDZA:%[a-zA-Z_0-9-]+]] = add nsw i32
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; DISABLE: [[RESZA:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDZA]] to i64
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; DISABLE: [[ADDB:%[a-zA-Z_0-9-]+]] = add nsw i32
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; DISABLE: [[RESB:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDB]] to i64
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;
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; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]])
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; OPTALL: ret
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define void @severalPromotions(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
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%ld = load i8, i8* %addr1
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%zextld = zext i8 %ld to i32
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%ld2 = load i32, i32* %addr2
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%add = add nsw i32 %ld2, %zextld
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%sextadd = sext i32 %add to i64
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%zexta = zext i8 %a to i32
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%addza = add nsw i32 %zexta, %zextld
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%sextaddza = sext i32 %addza to i64
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%addb = add nsw i32 %b, %zextld
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%sextaddb = sext i32 %addb to i64
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call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
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ret void
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|
}
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|
|
|
declare void @dummy(i64, i64, i64)
|
|
|
|
; Make sure we do not try to promote vector types since the type promotion
|
|
; helper does not support them for now.
|
|
; OPTALL-LABEL: @vectorPromotion
|
|
; OPTALL: [[SHL:%[a-zA-Z_0-9-]+]] = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
|
|
; OPTALL: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext <2 x i32> [[SHL]] to <2 x i64>
|
|
; OPTALL: ret
|
|
define void @vectorPromotion() {
|
|
entry:
|
|
%a = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
|
|
%b = zext <2 x i32> %a to <2 x i64>
|
|
ret void
|
|
}
|
|
|
|
@a = common global i32 0, align 4
|
|
@c = common global [2 x i32] zeroinitializer, align 4
|
|
|
|
; PR21978.
|
|
; Make sure we support promotion of operands that produces a Value as opposed
|
|
; to an instruction.
|
|
; This used to cause a crash.
|
|
; OPTALL-LABEL: @promotionOfArgEndsUpInValue
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16, i16* %addr
|
|
|
|
; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
|
|
; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i32)
|
|
;
|
|
; DISABLE-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw nsw i16 [[LD]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
|
|
; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
|
|
;
|
|
; OPTALL-NEXT: ret i32 [[RES]]
|
|
define i32 @promotionOfArgEndsUpInValue(i16* %addr) {
|
|
entry:
|
|
%val = load i16, i16* %addr
|
|
%add = add nuw nsw i16 %val, zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16)
|
|
%conv3 = sext i16 %add to i32
|
|
ret i32 %conv3
|
|
}
|
|
|
|
; Check that we see that one zext can be derived from the other for free.
|
|
; OPTALL-LABEL: @promoteTwoArgZextWithSourceExtendedTwice
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
|
|
|
|
; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
|
|
; OPT-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], 12
|
|
; OPT-NEXT: store i32 [[RES32]], i32* %addr
|
|
; OPT-NEXT: store i64 [[RES64]], i64* %q
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[RES2_32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], 12
|
|
; DISABLE-NEXT: store i32 [[RES32]], i32* %addr
|
|
; DISABLE-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES2_32]] to i64
|
|
; DISABLE-NEXT: store i64 [[ZEXT64]], i64* %q
|
|
;
|
|
; OPTALL-NEXT: ret void
|
|
define void @promoteTwoArgZextWithSourceExtendedTwice(i8* %p, i64* %q, i32 %b, i32* %addr) {
|
|
entry:
|
|
%t = load i8, i8* %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nuw i32 %zextt, %b
|
|
%add2 = add nuw i32 %zextt, 12
|
|
store i32 %add, i32 *%addr
|
|
%s = zext i32 %add2 to i64
|
|
store i64 %s, i64* %q
|
|
ret void
|
|
}
|