mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
179 lines
7.9 KiB
LLVM
179 lines
7.9 KiB
LLVM
; RUN: llc -march=x86-64 < %s > /dev/null
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; ScalarEvolution misses an opportunity to fold ((trunc x) + (trunc -x) + y),
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; but LSR should tolerate this.
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; rdar://7886751
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin11.0"
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define fastcc void @formatValue(i64 %arg5) nounwind {
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bb12: ; preds = %bb11
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%t = trunc i64 %arg5 to i32 ; <i32> [#uses=1]
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%t13 = sub i64 0, %arg5 ; <i64> [#uses=1]
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%t14 = and i64 %t13, 4294967295 ; <i64> [#uses=1]
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br label %bb15
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bb15: ; preds = %bb21, %bb12
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%t16 = phi i64 [ 0, %bb12 ], [ %t23, %bb15 ] ; <i64> [#uses=2]
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%t17 = mul i64 %t14, %t16 ; <i64> [#uses=1]
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%t18 = add i64 undef, %t17 ; <i64> [#uses=1]
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%t19 = trunc i64 %t18 to i32 ; <i32> [#uses=1]
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%t22 = icmp eq i32 %t19, %t ; <i1> [#uses=1]
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%t23 = add i64 %t16, 1 ; <i64> [#uses=1]
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br i1 %t22, label %bb24, label %bb15
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bb24: ; preds = %bb21, %bb11
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unreachable
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}
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; ScalarEvolution should be able to correctly expand the crazy addrec here.
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; PR6914
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define void @int323() nounwind {
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entry:
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br label %for.cond
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for.cond: ; preds = %lbl_264, %for.inc, %entry
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%g_263.tmp.1 = phi i8 [ undef, %entry ], [ %g_263.tmp.1, %for.cond ]
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%p_95.addr.0 = phi i8 [ 0, %entry ], [ %add, %for.cond ]
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%add = add i8 %p_95.addr.0, 1 ; <i8> [#uses=1]
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br i1 undef, label %for.cond, label %lbl_264
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lbl_264: ; preds = %if.end, %lbl_264.preheader
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%g_263.tmp.0 = phi i8 [ %g_263.tmp.1, %for.cond ] ; <i8> [#uses=1]
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%tmp7 = load i16, i16* undef ; <i16> [#uses=1]
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%conv8 = trunc i16 %tmp7 to i8 ; <i8> [#uses=1]
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%mul.i = mul i8 %p_95.addr.0, %p_95.addr.0 ; <i8> [#uses=1]
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%mul.i18 = mul i8 %mul.i, %conv8 ; <i8> [#uses=1]
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%tobool12 = icmp eq i8 %mul.i18, 0 ; <i1> [#uses=1]
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unreachable
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}
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; LSR ends up going into conservative pruning mode; don't prune the solution
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; so far that it becomes unsolvable though.
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; PR7077
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%struct.Bu = type { i32, i32, i32 }
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define void @_Z3fooP2Bui(%struct.Bu* nocapture %bu) {
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entry:
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br label %for.body
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for.body: ; preds = %for.inc131, %entry
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%indvar = phi i64 [ %indvar.next, %for.inc131 ], [ 0, %entry ] ; <i64> [#uses=3]
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br i1 undef, label %for.inc131, label %lor.lhs.false
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lor.lhs.false: ; preds = %for.body
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%tmp15 = add i64 %indvar, 1 ; <i64> [#uses=1]
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%tmp17 = add i64 %indvar, 2 ; <i64> [#uses=1]
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%tmp19 = add i64 %indvar, 3 ; <i64> [#uses=1]
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%tmp21 = add i64 %indvar, 4 ; <i64> [#uses=1]
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%tmp23 = add i64 %indvar, 5 ; <i64> [#uses=1]
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%tmp25 = add i64 %indvar, 6 ; <i64> [#uses=1]
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%tmp27 = add i64 %indvar, 7 ; <i64> [#uses=1]
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%tmp29 = add i64 %indvar, 8 ; <i64> [#uses=1]
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%tmp31 = add i64 %indvar, 9 ; <i64> [#uses=1]
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%tmp35 = add i64 %indvar, 11 ; <i64> [#uses=1]
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%tmp37 = add i64 %indvar, 12 ; <i64> [#uses=1]
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%tmp39 = add i64 %indvar, 13 ; <i64> [#uses=1]
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%tmp41 = add i64 %indvar, 14 ; <i64> [#uses=1]
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%tmp43 = add i64 %indvar, 15 ; <i64> [#uses=1]
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%tmp45 = add i64 %indvar, 16 ; <i64> [#uses=1]
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%tmp47 = add i64 %indvar, 17 ; <i64> [#uses=1]
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%mul = trunc i64 %indvar to i32 ; <i32> [#uses=1]
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%add22 = trunc i64 %tmp15 to i32 ; <i32> [#uses=1]
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%add28 = trunc i64 %tmp17 to i32 ; <i32> [#uses=1]
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%add34 = trunc i64 %tmp19 to i32 ; <i32> [#uses=1]
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%add40 = trunc i64 %tmp21 to i32 ; <i32> [#uses=1]
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%add46 = trunc i64 %tmp23 to i32 ; <i32> [#uses=1]
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%add52 = trunc i64 %tmp25 to i32 ; <i32> [#uses=1]
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%add58 = trunc i64 %tmp27 to i32 ; <i32> [#uses=1]
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%add64 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1]
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%add70 = trunc i64 %tmp31 to i32 ; <i32> [#uses=1]
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%add82 = trunc i64 %tmp35 to i32 ; <i32> [#uses=1]
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%add88 = trunc i64 %tmp37 to i32 ; <i32> [#uses=1]
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%add94 = trunc i64 %tmp39 to i32 ; <i32> [#uses=1]
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%add100 = trunc i64 %tmp41 to i32 ; <i32> [#uses=1]
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%add106 = trunc i64 %tmp43 to i32 ; <i32> [#uses=1]
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%add112 = trunc i64 %tmp45 to i32 ; <i32> [#uses=1]
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%add118 = trunc i64 %tmp47 to i32 ; <i32> [#uses=1]
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%tmp10 = getelementptr %struct.Bu, %struct.Bu* %bu, i64 %indvar, i32 2 ; <i32*> [#uses=1]
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%tmp11 = load i32, i32* %tmp10 ; <i32> [#uses=0]
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tail call void undef(i32 %add22)
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tail call void undef(i32 %add28)
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tail call void undef(i32 %add34)
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tail call void undef(i32 %add40)
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tail call void undef(i32 %add46)
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tail call void undef(i32 %add52)
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tail call void undef(i32 %add58)
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tail call void undef(i32 %add64)
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tail call void undef(i32 %add70)
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tail call void undef(i32 %add82)
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tail call void undef(i32 %add88)
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tail call void undef(i32 %add94)
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tail call void undef(i32 %add100)
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tail call void undef(i32 %add106)
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tail call void undef(i32 %add112)
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tail call void undef(i32 %add118)
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br label %for.body123
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for.body123: ; preds = %for.body123, %lor.lhs.false
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%j.03 = phi i32 [ 0, %lor.lhs.false ], [ %inc, %for.body123 ] ; <i32> [#uses=2]
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%add129 = add i32 %mul, %j.03 ; <i32> [#uses=1]
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tail call void undef(i32 %add129)
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%inc = add nsw i32 %j.03, 1 ; <i32> [#uses=1]
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br i1 undef, label %for.inc131, label %for.body123
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for.inc131: ; preds = %for.body123, %for.body
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%indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
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br i1 undef, label %for.end134, label %for.body
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for.end134: ; preds = %for.inc131
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ret void
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}
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; LSR needs to remember inserted instructions even in postinc mode, because
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; there could be multiple subexpressions within a single expansion which
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; require insert point adjustment.
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; PR7306
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define fastcc i32 @GetOptimum() nounwind {
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bb:
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br label %bb1
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bb1: ; preds = %bb1, %bb
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%t = phi i32 [ 0, %bb ], [ %t2, %bb1 ] ; <i32> [#uses=1]
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%t2 = add i32 %t, undef ; <i32> [#uses=3]
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br i1 undef, label %bb1, label %bb3
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bb3: ; preds = %bb1
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%t4 = add i32 undef, -1 ; <i32> [#uses=1]
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br label %bb5
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bb5: ; preds = %bb16, %bb3
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%t6 = phi i32 [ %t17, %bb16 ], [ 0, %bb3 ] ; <i32> [#uses=3]
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%t7 = add i32 undef, %t6 ; <i32> [#uses=2]
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%t8 = add i32 %t4, %t6 ; <i32> [#uses=1]
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br i1 undef, label %bb9, label %bb10
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bb9: ; preds = %bb5
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br label %bb10
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bb10: ; preds = %bb9, %bb5
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br i1 undef, label %bb11, label %bb16
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bb11: ; preds = %bb10
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%t12 = icmp ugt i32 %t7, %t2 ; <i1> [#uses=1]
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%t13 = select i1 %t12, i32 %t2, i32 %t7 ; <i32> [#uses=1]
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br label %bb14
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bb14: ; preds = %bb11
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store i32 %t13, i32* null
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ret i32 %t8
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bb16: ; preds = %bb10
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%t17 = add i32 %t6, 1 ; <i32> [#uses=1]
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br label %bb5
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}
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