llvm-6502/lib/CodeGen
Chris Lattner 4c6741f707 use Mang->getSymbol() more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15 20:37:38 +00:00
..
AsmPrinter Emit dwarf variable info communicated by code generator through DBG_VALUE machine instructions. 2010-03-15 18:33:46 +00:00
PBQP Fix various doxygen warnings. 2010-02-22 04:10:52 +00:00
SelectionDAG Create SDDbgValue for dbg_value intrinsics and remember its connections with DAG nodes. 2010-03-15 19:15:44 +00:00
AggressiveAntiDepBreaker.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
AggressiveAntiDepBreaker.h
AntiDepBreaker.h
BranchFolding.cpp eliminate InvalidateLabel and LabelIDList from MMI and replace 2010-03-14 02:24:55 +00:00
BranchFolding.h
CalcSpillWeights.cpp Always normalize spill weights, also for intervals created by spilling. 2010-02-18 21:33:05 +00:00
CMakeLists.txt Add file to CMakeLists.txt 2010-03-02 02:49:43 +00:00
CodePlacementOpt.cpp Make CodePlacementOpt detect special EH control flow by 2010-02-18 21:25:53 +00:00
CriticalAntiDepBreaker.cpp Fix some more places where dbg_value affected codegen. 2010-03-05 00:02:59 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Swap parameters of isSafeToMove and isSafeToReMat for consistency. 2010-03-02 19:03:01 +00:00
DwarfEHPrepare.cpp
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h change EH related stuff (other than EH_LABEL) to use MCSymbol 2010-03-14 01:41:15 +00:00
ELFWriter.cpp give Mangler access to TargetData. 2010-03-12 20:47:28 +00:00
ELFWriter.h
ExactHazardRecognizer.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
ExactHazardRecognizer.h
GCMetadata.cpp switch GC_LABEL to use an MCSymbol operand instead of a label ID operand. 2010-03-14 07:27:07 +00:00
GCMetadataPrinter.cpp Remove pointless forward declaration, MSVC got confused by this. 2010-03-14 22:00:28 +00:00
GCStrategy.cpp Change this code to allocate temporary labels from mccontext, 2010-03-14 07:29:45 +00:00
IfConversion.cpp
IntrinsicLowering.cpp Uniformize the names of type predicates: rather than having isFloatTy and 2010-02-15 16:12:20 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp The check for coalescing a virtual register to a physical register, e.g. 2010-03-11 08:20:21 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Better handling of dead super registers in LiveVariables. We used to do this: 2010-03-05 21:49:17 +00:00
LLVMTargetMachine.cpp rearrange MCContext ownership. Before LLVMTargetMachine created it 2010-03-13 20:55:24 +00:00
LowerSubregs.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
MachineBasicBlock.cpp eliminate the now-unneeded context argument of MBB::getSymbol() 2010-03-13 21:04:28 +00:00
MachineCSE.cpp Fix debug_value handling. 2010-03-11 02:10:24 +00:00
MachineDominators.cpp
MachineFunction.cpp rearrange MCContext ownership. Before LLVMTargetMachine created it 2010-03-13 20:55:24 +00:00
MachineFunctionAnalysis.cpp rearrange MCContext ownership. Before LLVMTargetMachine created it 2010-03-13 20:55:24 +00:00
MachineFunctionPass.cpp
MachineInstr.cpp add support for MCSymbols as operands to MachineInstrs. 2010-03-13 08:14:18 +00:00
MachineLICM.cpp - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. 2010-03-03 01:44:33 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Fix the case when a reference to an address taken BB is emitted in one 2010-03-15 19:09:43 +00:00
MachineModuleInfoImpls.cpp Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that 2010-03-10 22:34:10 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse. 2010-03-03 21:18:38 +00:00
MachineSink.cpp Fix some more places where dbg_value affected codegen. 2010-03-05 00:02:59 +00:00
MachineSSAUpdater.cpp fix missing #includes. 2010-02-10 01:17:36 +00:00
MachineVerifier.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
OptimizePHIs.cpp Besides removing phi cycles that reduce to a single value, also remove dead 2010-02-13 00:31:44 +00:00
Passes.cpp Uniformize the way these options are printed. Requested by 2010-02-18 14:37:52 +00:00
PHIElimination.cpp Remove PHINodeTraits and use MachineInstrExpressionTrait instead. 2010-03-03 23:55:49 +00:00
PHIElimination.h Remove PHINodeTraits and use MachineInstrExpressionTrait instead. 2010-03-03 23:55:49 +00:00
PostRASchedulerList.cpp Fix some more places where dbg_value affected codegen. 2010-03-05 00:02:59 +00:00
PreAllocSplitting.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
ProcessImplicitDefs.cpp Fix PR6300. 2010-02-15 22:03:29 +00:00
PrologEpilogInserter.cpp Clear up the last (famous last words) frame index value reuse issues for Thumb1. 2010-03-10 00:13:42 +00:00
PrologEpilogInserter.h Clear up the last (famous last words) frame index value reuse issues for Thumb1. 2010-03-10 00:13:42 +00:00
PseudoSourceValue.cpp Fix memcheck-found leaks: one false positive from using new[], and one true 2010-03-04 22:15:01 +00:00
README.txt
RegAllocLinearScan.cpp Remove dead code 2010-02-26 21:09:20 +00:00
RegAllocLocal.cpp Reapply 96294; now that I've gotten around to looking 2010-02-16 01:27:47 +00:00
RegAllocPBQP.cpp Remove terminating dot in description. Inconsistency pointed 2010-02-18 14:10:41 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp Progress towards shepherding debug info through SelectionDAG. 2010-03-10 22:13:47 +00:00
ScheduleDAGInstrs.h Progress towards shepherding debug info through SelectionDAG. 2010-03-10 22:13:47 +00:00
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp The check for coalescing a virtual register to a physical register, e.g. 2010-03-11 08:20:21 +00:00
SimpleRegisterCoalescing.h
SjLjEHPrepare.cpp For SJLJ exception handling, make sure that all calls that are not marked 2010-03-04 22:07:46 +00:00
SlotIndexes.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
Spiller.cpp
Spiller.h
StackProtector.cpp Uniformize the names of type predicates: rather than having isFloatTy and 2010-02-15 16:12:20 +00:00
StackSlotColoring.cpp move target-independent opcodes out of TargetInstrInfo 2010-02-09 19:54:29 +00:00
StrongPHIElimination.cpp Fix "the the" and similar typos. 2010-02-10 16:03:48 +00:00
TailDuplication.cpp eliminate InvalidateLabel and LabelIDList from MMI and replace 2010-03-14 02:24:55 +00:00
TargetInstrInfoImpl.cpp - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. 2010-03-03 01:44:33 +00:00
TargetLoweringObjectFileImpl.cpp use Mang->getSymbol() more. 2010-03-15 20:37:38 +00:00
TwoAddressInstructionPass.cpp Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse. 2010-03-03 21:18:38 +00:00
UnreachableBlockElim.cpp revert r98550, it isn't necessary or sufficient. 2010-03-15 18:42:01 +00:00
VirtRegMap.cpp Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl(). 2010-02-26 21:09:24 +00:00
VirtRegMap.h
VirtRegRewriter.cpp Extract methods from LocalRewriter::RewriteMBB bringing it down to 666 lines. 2010-03-11 23:04:34 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.