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b0cf29c5cf
the comments in FastISelEmitter.cpp for details on what this is. This is currently experimental and unusable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54751 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.4 KiB
C++
72 lines
2.4 KiB
C++
//===-- FastISel.h - Definition of the FastISel class ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the FastISel class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FASTISEL_H
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#define LLVM_CODEGEN_FASTISEL_H
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#include "llvm/BasicBlock.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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class MachineBasicBlock;
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class MachineFunction;
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class TargetInstrInfo;
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class TargetRegisterClass;
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/// This file defines the FastISel class. This is a fast-path instruction
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/// selection class that generates poor code and doesn't support illegal
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/// types or non-trivial lowering, but runs quickly.
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class FastISel {
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MachineBasicBlock *MBB;
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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public:
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FastISel(MachineBasicBlock *mbb, MachineFunction *mf,
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const TargetInstrInfo *tii)
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: MBB(mbb), MF(mf), TII(tii) {}
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/// SelectInstructions - Do "fast" instruction selection over the
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/// LLVM IR instructions in the range [Begin, N) where N is either
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/// End or the first unsupported instruction. Return N.
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/// ValueMap is filled in with a mapping of LLVM IR Values to
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/// register numbers.
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BasicBlock::iterator
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SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
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DenseMap<const Value*, unsigned> &ValueMap);
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protected:
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virtual unsigned FastEmit_(MVT::SimpleValueType VT,
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ISD::NodeType Opcode);
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virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
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ISD::NodeType Opcode, unsigned Op0);
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virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
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ISD::NodeType Opcode,
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unsigned Op0, unsigned Op1);
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unsigned FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC);
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unsigned FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0);
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unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1);
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};
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}
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#endif
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