mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
59ee62d241
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
3.2 KiB
C++
97 lines
3.2 KiB
C++
//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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using namespace llvm;
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void
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MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
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const SubtargetFeatureKV *PF,
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const SubtargetFeatureKV *PD,
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const SubtargetInfoKV *PI,
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const InstrStage *IS,
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const unsigned *OC,
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const unsigned *FP,
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unsigned NF, unsigned NP) {
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TargetTriple = TT;
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ProcFeatures = PF;
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ProcDesc = PD;
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ProcItins = PI;
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Stages = IS;
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OperandCycles = OC;
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ForwardingPathes = FP;
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NumFeatures = NF;
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NumProcs = NP;
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SubtargetFeatures Features(FS);
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FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
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ProcFeatures, NumFeatures);
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}
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/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
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/// feature string) and recompute feature bits.
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uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
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SubtargetFeatures Features(FS);
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FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
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ProcFeatures, NumFeatures);
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return FeatureBits;
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}
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version does not change the implied bits.
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uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
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FeatureBits ^= FB;
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return FeatureBits;
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}
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version will also change all implied bits.
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uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
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SubtargetFeatures Features;
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FeatureBits = Features.ToggleFeature(FeatureBits, FS,
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ProcFeatures, NumFeatures);
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return FeatureBits;
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}
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InstrItineraryData
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MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
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assert(ProcItins && "Instruction itineraries information not available!");
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#ifndef NDEBUG
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for (size_t i = 1; i < NumProcs; i++) {
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assert(strcmp(ProcItins[i - 1].Key, ProcItins[i].Key) < 0 &&
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"Itineraries table is not sorted");
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}
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#endif
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// Find entry
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SubtargetInfoKV KV;
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KV.Key = CPU.data();
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const SubtargetInfoKV *Found =
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std::lower_bound(ProcItins, ProcItins+NumProcs, KV);
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if (Found == ProcItins+NumProcs || StringRef(Found->Key) != CPU) {
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errs() << "'" << CPU
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<< "' is not a recognized processor for this target"
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<< " (ignoring processor)\n";
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return InstrItineraryData();
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}
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return InstrItineraryData(Stages, OperandCycles, ForwardingPathes,
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(InstrItinerary *)Found->Value);
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}
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