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https://github.com/c64scene-ar/llvm-6502.git
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ae43cab6ba
Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
3.0 KiB
C++
75 lines
3.0 KiB
C++
//===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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#ifndef R600ISELLOWERING_H
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#define R600ISELLOWERING_H
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#include "AMDGPUISelLowering.h"
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namespace llvm {
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class R600InstrInfo;
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class R600TargetLowering : public AMDGPUTargetLowering {
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public:
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R600TargetLowering(TargetMachine &TM);
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virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock * BB) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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void ReplaceNodeResults(SDNode * N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const;
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virtual SDValue LowerFormalArguments(
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SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const;
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private:
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unsigned Gen;
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/// Each OpenCL kernel has nine implicit parameters that are stored in the
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/// first nine dwords of a Vertex Buffer. These implicit parameters are
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/// lowered to load instructions which retrieve the values from the Vertex
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/// Buffer.
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SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
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SDLoc DL, unsigned DwordOffset) const;
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void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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MachineRegisterInfo & MRI, unsigned dword_offset) const;
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SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG) const;
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/// \brief Lower ROTL opcode to BITALIGN
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SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
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SelectionDAG &DAG) const;
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void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
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unsigned &Channel, unsigned &PtrIncr) const;
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bool isZero(SDValue Op) const;
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virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
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};
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} // End namespace llvm;
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#endif // R600ISELLOWERING_H
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