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233a60ec40
This introduces a new pass, SlotIndexes, which is responsible for numbering instructions for register allocation (and other clients). SlotIndexes numbering is designed to match the existing scheme, so this patch should not cause any changes in the generated code. For consistency, and to avoid naming confusion, LiveIndex has been renamed SlotIndex. The processImplicitDefs method of the LiveIntervals analysis has been moved into its own pass so that it can be run prior to SlotIndexes. This was necessary to match the existing numbering scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85979 91177308-0d34-0410-b5e6-96231b3b80d8
370 lines
12 KiB
C++
370 lines
12 KiB
C++
//===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "spiller"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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Spiller::~Spiller() {}
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namespace {
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/// Utility class for spillers.
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class SpillerBase : public Spiller {
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protected:
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MachineFunction *mf;
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LiveIntervals *lis;
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LiveStacks *ls;
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MachineFrameInfo *mfi;
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MachineRegisterInfo *mri;
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const TargetInstrInfo *tii;
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VirtRegMap *vrm;
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/// Construct a spiller base.
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SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls,
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VirtRegMap *vrm) :
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mf(mf), lis(lis), ls(ls), vrm(vrm)
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{
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mfi = mf->getFrameInfo();
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mri = &mf->getRegInfo();
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tii = mf->getTarget().getInstrInfo();
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}
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/// Ensures there is space before the given machine instruction, returns the
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/// instruction's new number.
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SlotIndex makeSpaceBefore(MachineInstr *mi) {
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if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
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// FIXME: Should be updated to use rewrite-in-place methods when they're
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// introduced. Currently broken.
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//lis->scaleNumbering(2);
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//ls->scaleNumbering(2);
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}
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SlotIndex miIdx = lis->getInstructionIndex(mi);
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assert(lis->hasGapBeforeInstr(miIdx));
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return miIdx;
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}
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/// Ensure there is space after the given machine instruction, returns the
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/// instruction's new number.
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SlotIndex makeSpaceAfter(MachineInstr *mi) {
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if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) {
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// FIXME: Should be updated to use rewrite-in-place methods when they're
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// introduced. Currently broken.
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// lis->scaleNumbering(2);
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// ls->scaleNumbering(2);
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}
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SlotIndex miIdx = lis->getInstructionIndex(mi);
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assert(lis->hasGapAfterInstr(miIdx));
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return miIdx;
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}
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/// Insert a store of the given vreg to the given stack slot immediately
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/// after the given instruction. Returns the base index of the inserted
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/// instruction. The caller is responsible for adding an appropriate
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/// LiveInterval to the LiveIntervals analysis.
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SlotIndex insertStoreAfter(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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MachineBasicBlock::iterator nextInstItr(next(mi));
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SlotIndex miIdx = makeSpaceAfter(mi);
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tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg,
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true, ss, trc);
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MachineBasicBlock::iterator storeInstItr(next(mi));
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MachineInstr *storeInst = &*storeInstItr;
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SlotIndex storeInstIdx = miIdx.getNextIndex();
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assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
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"Store inst index already in use.");
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lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
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return storeInstIdx;
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}
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/// Insert a store of the given vreg to the given stack slot immediately
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/// before the given instructnion. Returns the base index of the inserted
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/// Instruction.
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SlotIndex insertStoreBefore(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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SlotIndex miIdx = makeSpaceBefore(mi);
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tii->storeRegToStackSlot(*mi->getParent(), mi, vreg, true, ss, trc);
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MachineBasicBlock::iterator storeInstItr(prior(mi));
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MachineInstr *storeInst = &*storeInstItr;
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SlotIndex storeInstIdx = miIdx.getPrevIndex();
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assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
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"Store inst index already in use.");
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lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
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return storeInstIdx;
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}
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void insertStoreAfterInstOnInterval(LiveInterval *li,
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MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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SlotIndex storeInstIdx = insertStoreAfter(mi, ss, vreg, trc);
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SlotIndex start = lis->getInstructionIndex(mi).getDefIndex(),
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end = storeInstIdx.getUseIndex();
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VNInfo *vni =
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li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator());
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vni->addKill(storeInstIdx);
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DEBUG(errs() << " Inserting store range: [" << start
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<< ", " << end << ")\n");
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LiveRange lr(start, end, vni);
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li->addRange(lr);
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}
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/// Insert a load of the given vreg from the given stack slot immediately
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/// after the given instruction. Returns the base index of the inserted
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/// instruction. The caller is responsibel for adding/removing an appropriate
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/// range vreg's LiveInterval.
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SlotIndex insertLoadAfter(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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MachineBasicBlock::iterator nextInstItr(next(mi));
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SlotIndex miIdx = makeSpaceAfter(mi);
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tii->loadRegFromStackSlot(*mi->getParent(), nextInstItr, vreg, ss, trc);
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MachineBasicBlock::iterator loadInstItr(next(mi));
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MachineInstr *loadInst = &*loadInstItr;
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SlotIndex loadInstIdx = miIdx.getNextIndex();
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assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
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"Store inst index already in use.");
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lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
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return loadInstIdx;
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}
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/// Insert a load of the given vreg from the given stack slot immediately
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/// before the given instruction. Returns the base index of the inserted
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/// instruction. The caller is responsible for adding an appropriate
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/// LiveInterval to the LiveIntervals analysis.
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SlotIndex insertLoadBefore(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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SlotIndex miIdx = makeSpaceBefore(mi);
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tii->loadRegFromStackSlot(*mi->getParent(), mi, vreg, ss, trc);
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MachineBasicBlock::iterator loadInstItr(prior(mi));
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MachineInstr *loadInst = &*loadInstItr;
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SlotIndex loadInstIdx = miIdx.getPrevIndex();
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assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
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"Load inst index already in use.");
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lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
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return loadInstIdx;
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}
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void insertLoadBeforeInstOnInterval(LiveInterval *li,
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MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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SlotIndex loadInstIdx = insertLoadBefore(mi, ss, vreg, trc);
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SlotIndex start = loadInstIdx.getDefIndex(),
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end = lis->getInstructionIndex(mi).getUseIndex();
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VNInfo *vni =
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li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator());
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vni->addKill(lis->getInstructionIndex(mi));
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DEBUG(errs() << " Intserting load range: [" << start
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<< ", " << end << ")\n");
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LiveRange lr(start, end, vni);
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li->addRange(lr);
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}
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/// Add spill ranges for every use/def of the live interval, inserting loads
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/// immediately before each use, and stores after each def. No folding is
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/// attempted.
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std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
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DEBUG(errs() << "Spilling everywhere " << *li << "\n");
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assert(li->weight != HUGE_VALF &&
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"Attempting to spill already spilled value.");
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assert(!li->isStackSlot() &&
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"Trying to spill a stack slot.");
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DEBUG(errs() << "Trivial spill everywhere of reg" << li->reg << "\n");
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std::vector<LiveInterval*> added;
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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unsigned ss = vrm->assignVirt2StackSlot(li->reg);
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for (MachineRegisterInfo::reg_iterator
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regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
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MachineInstr *mi = &*regItr;
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DEBUG(errs() << " Processing " << *mi);
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do {
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++regItr;
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} while (regItr != mri->reg_end() && (&*regItr == mi));
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SmallVector<unsigned, 2> indices;
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bool hasUse = false;
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bool hasDef = false;
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for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
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MachineOperand &op = mi->getOperand(i);
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if (!op.isReg() || op.getReg() != li->reg)
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continue;
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hasUse |= mi->getOperand(i).isUse();
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hasDef |= mi->getOperand(i).isDef();
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indices.push_back(i);
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}
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unsigned newVReg = mri->createVirtualRegister(trc);
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vrm->grow();
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vrm->assignVirt2StackSlot(newVReg, ss);
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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newLI->weight = HUGE_VALF;
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for (unsigned i = 0; i < indices.size(); ++i) {
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mi->getOperand(indices[i]).setReg(newVReg);
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if (mi->getOperand(indices[i]).isUse()) {
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mi->getOperand(indices[i]).setIsKill(true);
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}
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}
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assert(hasUse || hasDef);
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if (hasUse) {
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insertLoadBeforeInstOnInterval(newLI, mi, ss, newVReg, trc);
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}
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if (hasDef) {
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insertStoreAfterInstOnInterval(newLI, mi, ss, newVReg, trc);
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}
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added.push_back(newLI);
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}
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return added;
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}
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};
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/// Spills any live range using the spill-everywhere method with no attempt at
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/// folding.
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class TrivialSpiller : public SpillerBase {
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public:
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TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls,
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VirtRegMap *vrm) :
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SpillerBase(mf, lis, ls, vrm) {}
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std::vector<LiveInterval*> spill(LiveInterval *li) {
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return trivialSpillEverywhere(li);
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}
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std::vector<LiveInterval*> intraBlockSplit(LiveInterval *li, VNInfo *valno) {
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std::vector<LiveInterval*> spillIntervals;
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if (!valno->isDefAccurate() && !valno->isPHIDef()) {
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// Early out for values which have no well defined def point.
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return spillIntervals;
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}
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// Ok.. we should be able to proceed...
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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unsigned ss = vrm->assignVirt2StackSlot(li->reg);
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vrm->grow();
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vrm->assignVirt2StackSlot(li->reg, ss);
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MachineInstr *mi = 0;
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SlotIndex storeIdx = SlotIndex();
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if (valno->isDefAccurate()) {
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// If we have an accurate def we can just grab an iterator to the instr
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// after the def.
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mi = lis->getInstructionFromIndex(valno->def);
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storeIdx = insertStoreAfter(mi, ss, li->reg, trc).getDefIndex();
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} else {
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// if we get here we have a PHI def.
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mi = &lis->getMBBFromIndex(valno->def)->front();
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storeIdx = insertStoreBefore(mi, ss, li->reg, trc).getDefIndex();
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}
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MachineBasicBlock *defBlock = mi->getParent();
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SlotIndex loadIdx = SlotIndex();
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// Now we need to find the load...
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MachineBasicBlock::iterator useItr(mi);
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for (; !useItr->readsRegister(li->reg); ++useItr) {}
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if (useItr != defBlock->end()) {
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MachineInstr *loadInst = useItr;
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loadIdx = insertLoadBefore(loadInst, ss, li->reg, trc).getUseIndex();
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}
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else {
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MachineInstr *loadInst = &defBlock->back();
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loadIdx = insertLoadAfter(loadInst, ss, li->reg, trc).getUseIndex();
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}
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li->removeRange(storeIdx, loadIdx, true);
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return spillIntervals;
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}
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};
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}
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llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
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LiveStacks *ls, VirtRegMap *vrm) {
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return new TrivialSpiller(mf, lis, ls, vrm);
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}
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