Tim Northover 03eecdccff FastISel: constrain the RegClass of operands when emitting instructions.
ARM64 suffered multiple -verify-machineinstr failures (principally over the
xsp/xzr issue) because FastISel was completely ignoring which subset of the
general-purpose registers each instruction required.

More fixes are coming in ARM64 specific FastISel, but this should cover the
generic problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206283 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 13:59:49 +00:00
2014-03-29 10:18:08 +00:00
2014-03-12 22:40:22 +00:00
2014-04-07 03:57:04 +00:00
2014-03-12 22:40:22 +00:00
2014-04-02 23:03:28 +00:00
2014-03-29 10:18:08 +00:00
2014-04-10 22:25:51 +00:00
2014-03-12 22:40:22 +00:00

Low Level Virtual Machine (LLVM)
================================

This directory and its subdirectories contain source code for the Low Level
Virtual Machine, a toolkit for the construction of highly optimized compilers,
optimizers, and runtime environments.

LLVM is open source software. You may freely distribute it under the terms of
the license agreement found in LICENSE.txt.

Please see the documentation provided in docs/ for further
assistance with LLVM, and in particular docs/GettingStarted.rst for getting
started with LLVM and docs/README.txt for an overview of LLVM's
documentation setup.

If you're writing a package for LLVM, see docs/Packaging.rst for our
suggestions.

Description
LLVM backend for 6502
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