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https://github.com/c64scene-ar/llvm-6502.git
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6824f127f9
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
215 lines
5.7 KiB
LLVM
215 lines
5.7 KiB
LLVM
; Test 64-bit conditional stores that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare void @foo(i64 *)
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; Test with the loaded value first.
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define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: %r2
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %alt, i64 %orig
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the high end of the aligned STG range.
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define void @f3(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, 524280(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 65535
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f4(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, 524288
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 65536
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the low end of the STG range.
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define void @f5(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, -524288(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 -65536
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, -524296
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 -65537
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check that STG allows an index.
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define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r4, 524287(%r3,%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check that volatile loads are not matched.
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define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f8:
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; CHECK: lg {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: stg {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load volatile i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; ...likewise stores. In this case we should have a conditional load into %r3.
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define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f9:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: lg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: stg %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store volatile i64 %res, i64 *%ptr
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ret void
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}
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; Check that atomic loads are not matched. The transformation is OK for
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; the "unordered" case tested here, but since we don't try to handle atomic
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; operations at all in this context, it seems better to assert that than
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; to restrict the test to a stronger ordering.
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define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
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; FIXME: should use a normal load instead of CSG.
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; CHECK-LABEL: f10:
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; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: stg {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load atomic i64 *%ptr unordered, align 8
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; ...likewise stores.
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define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
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; FIXME: should use a normal store instead of CSG.
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; CHECK-LABEL: f11:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: lg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: csg {{%r[0-5]}}, %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store atomic i64 %res, i64 *%ptr unordered, align 8
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ret void
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}
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; Try a frame index base.
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define void @f12(i64 %alt, i32 %limit) {
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; CHECK-LABEL: f12:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-NOT: %r15
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r15
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; CHECK: stg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: [[LABEL]]:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca i64
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call void @foo(i64 *%ptr)
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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call void @foo(i64 *%ptr)
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ret void
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}
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